If I have a signal called jim, which is a vector of, say, 7 downto 0 and in a clk'd process I make these assignments to this signal for a given a case condition :
when condition_true
-- set all bits to zero
jim <= (others => '0');
-- set bit 4 active to '1'
jim(4) <= '1';
...will jim have all bits set to '0' apart from bit 4. Jim is a signal.
I think it will and this works but in terms of synthese do you have to assign to others first and then assign the bits you want to change or does it not matter?
when condition_true
-- set all bits to zero
jim <= (others => '0');
-- set bit 4 active to '1'
jim(4) <= '1';
...will jim have all bits set to '0' apart from bit 4. Jim is a signal.
I think it will and this works but in terms of synthese do you have to assign to others first and then assign the bits you want to change or does it not matter?