others and unconstrained array

Discussion in 'VHDL' started by MariuszK, Nov 22, 2008.

  1. MariuszK

    MariuszK Guest

    Hello,

    I have following error in line "out1 <= (others=>'0');"
    BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
    array aggregate.

    If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
    everything work. How can I change below code to have universal
    unconstrained buffer with reset?

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    entity BuffG is
    port(
    CLK : in STD_LOGIC;
    RST : in STD_LOGIC;
    CE : in STD_LOGIC;
    in1 : in STD_LOGIC_Vector;
    out1: out STD_LOGIC_Vector
    );
    end BuffG;

    architecture BuffG of BuffG is
    begin
    process(CLK)
    begin
    if rising_edge(CLK) then
    if RST = '1' then
    out1 <= (others=>'0');
    elsif CE = '1' then
    out1 <= in1;
    end if;
    end if;
    end process;
    end BuffG;
     
    MariuszK, Nov 22, 2008
    #1
    1. Advertising

  2. MariuszK

    KJ Guest

    "MariuszK" <> wrote in message
    news:...
    > Hello,
    >
    > I have following error in line "out1 <= (others=>'0');"
    > BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
    > array aggregate.
    >
    > If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
    > everything work. How can I change below code to have universal
    > unconstrained buffer with reset?
    >


    One way would be by adding a function, either in the architecture or the
    process, see below.

    architecture BuffG of BuffG is
    begin
    process(CLK)
    function Zeroit(V: std_logic_vector) return std_logic_vector is
    variable RetVal: std_logic_vector(V'range) := (others => '0');
    begin
    return(RetVal);
    end function Zeroit;
    begin
    if rising_edge(CLK) then
    if RST = '1' then
    out1 <= (others=>'0');
    elsif CE = '1' then
    out1 <= in1;
    end if;
    end if;
    end process;
    end BuffG;

    KJ
     
    KJ, Nov 23, 2008
    #2
    1. Advertising

  3. MariuszK

    KJ Guest

    "MariuszK" <> wrote in message
    news:...
    > Hello,
    >
    > I have following error in line "out1 <= (others=>'0');"
    > BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
    > array aggregate.
    >
    > If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
    > everything work. How can I change below code to have universal
    > unconstrained buffer with reset?
    >


    Another method is to define a constant inside the process or architecture
    that is of the same size, see below.

    architecture BuffG of BuffG is
    begin
    process(CLK)
    constant Zeros: std_logic_vector(out1'range) := (others => '0');
    begin
    if rising_edge(CLK) then
    if RST = '1' then
    out1 <= Zeros;
    elsif CE = '1' then
    out1 <= in1;
    end if;
    end if;
    end process;
    end BuffG;

    KJ
     
    KJ, Nov 23, 2008
    #3
  4. MariuszK

    KJ Guest

    "MariuszK" <> wrote in message
    news:...
    > Hello,
    >
    > I have following error in line "out1 <= (others=>'0');"
    > BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
    > array aggregate.
    >
    > If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
    > everything work. How can I change below code to have universal
    > unconstrained buffer with reset?
    >


    One way would be by adding a function, either in the architecture or the
    process, see below.

    architecture BuffG of BuffG is
    begin
    process(CLK)
    function Zeroit(V: std_logic_vector) return std_logic_vector is
    variable RetVal: std_logic_vector(V'range) := (others => '0');
    begin
    return(RetVal);
    end function Zeroit;
    begin
    if rising_edge(CLK) then
    if RST = '1' then
    out1 <= Zeroit(out1);
    elsif CE = '1' then
    out1 <= in1;
    end if;
    end if;
    end process;
    end BuffG;

    KJ
     
    KJ, Nov 23, 2008
    #4
  5. MariuszK <> wrote in news:58dc006e-749f-46ef-
    :

    > Hello,
    >
    > I have following error in line "out1 <= (others=>'0');"
    > BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
    > array aggregate.
    >
    > If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
    > everything work. How can I change below code to have universal
    > unconstrained buffer with reset?
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    >
    > entity BuffG is
    > port(
    > CLK : in STD_LOGIC;
    > RST : in STD_LOGIC;
    > CE : in STD_LOGIC;
    > in1 : in STD_LOGIC_Vector;
    > out1: out STD_LOGIC_Vector
    > );
    > end BuffG;
    >
    > architecture BuffG of BuffG is
    > begin
    > process(CLK)
    > begin
    > if rising_edge(CLK) then
    > if RST = '1' then
    > out1 <= (others=>'0');
    > elsif CE = '1' then
    > out1 <= in1;
    > end if;
    > end if;
    > end process;
    > end BuffG;



    Change the line:
    out1 <= (others=>'0');

    to:
    out1 <= (out1'range =>'0');

    Regards,
    Allan
     
    Allan Herriman, Nov 23, 2008
    #5
  6. MariuszK

    MariuszK Guest

    On 23 Lis, 03:42, Allan Herriman <> wrote:
    > MariuszK <> wrote in news:58dc006e-749f-46ef-
    > :
    >
    >
    >
    >
    >
    > > Hello,

    >
    > > I have following error in line "out1 <= (others=>'0');"
    > > BuffG.vhd : (47, 22): Keyword "others" is not allowed in unconstrained
    > > array aggregate.

    >
    > > If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0)
    > > everything work. How can I change below code to have universal
    > > unconstrained buffer with reset?

    >
    > > library IEEE;
    > > use IEEE.STD_LOGIC_1164.all;

    >
    > > entity BuffG is
    > >    port(
    > >       CLK : in  STD_LOGIC;
    > >       RST : in  STD_LOGIC;
    > >       CE  : in  STD_LOGIC;
    > >       in1 : in  STD_LOGIC_Vector;
    > >       out1: out STD_LOGIC_Vector
    > >       );
    > > end BuffG;

    >
    > > architecture BuffG of BuffG is
    > > begin
    > >    process(CLK)
    > >    begin
    > >       if rising_edge(CLK) then
    > >          if RST = '1' then
    > >             out1 <= (others=>'0');
    > >          elsif CE = '1' then
    > >             out1 <= in1;
    > >          end if;
    > >       end if;
    > >    end process;
    > > end BuffG;

    >
    > Change the line:
    >             out1 <= (others=>'0');
    >
    > to:
    >             out1 <= (out1'range =>'0');
    >
    > Regards,
    > Allan- Ukryj cytowany tekst -
    >
    > - Poka¿ cytowany tekst -


    Thank you All!
    Attribute "'range" that's it what I need.

    Best Regards,
    Mariusz
     
    MariuszK, Nov 23, 2008
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. FE
    Replies:
    0
    Views:
    1,680
  2. Amal
    Replies:
    5
    Views:
    8,884
    Brandon
    Mar 8, 2006
  3. Nicolas Matringe

    Unconstrained array and range direction

    Nicolas Matringe, Oct 2, 2006, in forum: VHDL
    Replies:
    12
    Views:
    1,225
  4. jens
    Replies:
    3
    Views:
    905
  5. Travis
    Replies:
    3
    Views:
    417
Loading...

Share This Page