overflow with signed and unsigned values

Z

Zaki

Hello,

I want to design an ALU with signed and unsigned addition.
The problem is the overflow:

SIGNAL Sum : STD_LOGIC_VECTOR( 8 DOWNTO 0 );
SIGNAL ALU_output_mux : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Ainput, Binput : STD_LOGIC_VECTOR( 7 DOWNTO 0 );

Sum <= unsigned('0' & Ainput) + unsigned('0' & Binput);
ALU_output_mux <= Sum(7 DOWNTO 0) ;
Overflow <= Sum(8);

Overflow would be '1' when Sum is bigger than 255.
This works for unsigned addition well but I need that overflow for signed
values.
Why I cant write:

Overflow <= '1' when (Sum >= 128 or Sum < 127) else
'0';

Can someone help me?

Thx
 
N

Nicolas Matringe

Zaki a écrit:
Why I cant write:

Overflow <= '1' when (Sum >= 128 or Sum < 127) else
'0';

Can someone help me?

Your condition looks like it is always true. Maybe you should write "Sum
< -127" ?
 
E

Egbert Molenkamp

"Sum" is declared as std_logic_vector.
I don't think the "<=" is overloaded for left operand of this type and right
operand of type (un)signed.
Change type of SUM in SIGNED(8 downto 0); (Since you want twoscomplement)
Then a type conversion is needed for the ALU_output_mux:
ALU_output_mux <= std_logic_vector( Sum(7 DOWNTO 0) );
Finally, as mentioned by Nicolas
Sum >= 128 or Sum < 127
is a little bit funny. In twoscomplement the most negative value is -128 and
most positive 127
so this should be something like:
Sum >= 128 or Sum <= -129

An alternative solution (without extension of the operands). Look at the
sign bits:
overflow <= '1' when (Ainput(7)=Binput(7)) and (Ainput(7)/=Sum(7)) ELSE
'0';

Egbert Molenkamp
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

No members online now.

Forum statistics

Threads
473,743
Messages
2,569,478
Members
44,898
Latest member
BlairH7607

Latest Threads

Top