Overriding functionality of an entity is prohibited?

Discussion in 'VHDL' started by Valentin Tihomirov, Nov 2, 2003.

  1. I want to extend behaviour(architecture) of an entity (interface).

    architecture EXTENDING_ARCH of SOME_ENTITY is
    begin
    base: entity work.SOME_ENTITY(BASIC_ARCH) PORT MAP(

    Error message: "Entity 'SOME_ENTITY' is exactly the same as instance (same
    ports and generics)."
    Valentin Tihomirov, Nov 2, 2003
    #1
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  2. Valentin Tihomirov wrote:

    > I want to extend behaviour(architecture) of an entity (interface).
    >
    > architecture EXTENDING_ARCH of SOME_ENTITY is
    > begin
    > base: entity work.SOME_ENTITY(BASIC_ARCH) PORT MAP(
    >
    > Error message: "Entity 'SOME_ENTITY' is exactly the same as instance
    > (same ports and generics)."


    I have no idea whether the above is allowed or not.

    In stead of direct instantiation, you could use a component
    instantiation and use a configuration declaration (or even
    specification) to specifiy the architecture you want to use
    (basic_arch in your case).

    Something along these lines (untested):

    ENTITY some_entity IS
    END ENTITY some_entity.

    ARCHITECTURE basic_arch OF some_entity IS
    BEGIN
    END ARCHITECTURE basic_arch;

    ARCHITECTURE extending_arch OF some_entity IS
    COMPONENT some_entity IS
    END COMPONENT some_entity;
    BEGIN
    base: some_entity
    PORT MAP
    (
    ...
    );
    END ARCHITECTURE extending_arch;

    CONFIGURATION some_entity_extending_arch_cfg OF some_entity IS
    FOR extending_arch
    FOR base
    USE ENTITY work.some_entity(base_arch);
    END FOR;
    END FOR;
    END CONFIGURATION some_entity_extending_arch_cfg;

    --
    Paul.
    (s and x switched in e-mail)
    Paul Uiterlinden, Nov 2, 2003
    #2
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  3. Component instantiations are used for components which structural or
    behavioral implementation is not yes defined. In my case I base new
    architecture on a specific one. I wanted someone to explain where is the
    circullar reference I encounter, where is my fault?
    Valentin Tihomirov, Nov 2, 2003
    #3
  4. Valentin Tihomirov wrote:
    > Component instantiations are used for components which structural or
    > behavioral implementation is not yes defined. In my case I base new
    > architecture on a specific one. I wanted someone to explain where is the
    > circullar reference I encounter, where is my fault?


    Consider a new name for the expanded entity:

    architecture synth of SOME_ENTITY_PLUS is
    begin
    base: entity work.SOME_ENTITY(synth) PORT MAP(

    -- Mike Treseler
    Mike Treseler, Nov 2, 2003
    #4
  5. Valentin Tihomirov

    Klaus Falser Guest

    In article <bo3glc$17aoqq$-berlin.de>, says...
    > Component instantiations are used for components which structural or
    > behavioral implementation is not yes defined. In my case I base new
    > architecture on a specific one. I wanted someone to explain where is the
    > circullar reference I encounter, where is my fault?
    >


    Your line

    base: entity work.SOME_ENTITY(BASIC_ARCH) PORT MAP(..

    is only an abbreviation for a component declaration and an instantiation together.

    It creates the same entity internally of the entity.

    Immagine your entity declatation as a socket and the architectures as the different
    pin-compatible devices which can be plugged in.

    You can not have a device which has internally a socket for the same device, or at
    least it is hard to deal with.
    What happens if you plug in the same device in the internal socket again and again?

    If you want to define an extended entity, you have to give it a new name.

    Do not forget that VHDL is a hardware description language and not a programming
    language!

    Best regards

    --
    Klaus Falser
    Durst Phototechnik AG
    Klaus Falser, Nov 3, 2003
    #5
  6. Klaus Falser wrote:
    >
    > Your line
    >
    > base: entity work.SOME_ENTITY(BASIC_ARCH) PORT MAP(..
    >
    > is only an abbreviation for a component declaration and an instantiation together.
    >
    > It creates the same entity internally of the entity.
    >
    > Immagine your entity declatation as a socket and the architectures as the different
    > pin-compatible devices which can be plugged in.
    >
    > You can not have a device which has internally a socket for the same device, or at
    > least it is hard to deal with.
    > What happens if you plug in the same device in the internal socket again and again?


    But that does not happen. In architecture BASIC_ARCH there is no further
    instantiation.

    Paul.
    Paul Uiterlinden, Nov 3, 2003
    #6
  7. yes, glad to see one careful person

    Yes, BASIC_ARCH does not have any instantiations.
    Valentin Tihomirov, Nov 3, 2003
    #7
  8. "Klaus Falser" <> wrote in message
    news:MPG.1a102f1715aea6d598969d@151.99.250.3...
    > In article <bo3glc$17aoqq$-berlin.de>,

    says...
    > > Component instantiations are used for components which structural or
    > > behavioral implementation is not yes defined. In my case I base new
    > > architecture on a specific one. I wanted someone to explain where is the
    > > circullar reference I encounter, where is my fault?
    > >

    >
    > Your line
    >
    > base: entity work.SOME_ENTITY(BASIC_ARCH) PORT MAP(..
    >
    > is only an abbreviation for a component declaration and an instantiation

    together.
    >
    > It creates the same entity internally of the entity.
    >
    > Immagine your entity declatation as a socket and the architectures as the

    different
    > pin-compatible devices which can be plugged in.
    >
    > You can not have a device which has internally a socket for the same

    device, or at
    > least it is hard to deal with.
    > What happens if you plug in the same device in the internal socket again

    and again?
    >
    > If you want to define an extended entity, you have to give it a new name.
    >
    > Do not forget that VHDL is a hardware description language and not a

    programming
    > language!
    >


    Where did I confuse programming and HW desc. languages? Nevertheless, there
    are definite analogues to OOP. An entity corresponds to interface,
    architectures allow for several implementations of that interface. These are
    VHDL components that stand for sockets; meantime, I instantiate a specific
    architecture and compiler should not get into instantiation recursion when
    analyzes VHDL properly because the nested architecture does not instantiate
    anything.

    Thank you for your view of entity notion. Here was mine. May be
    compiler/simulator has a third notion of entity object. Where is a supreme
    arbiter that can tell who is right?
    Valentin Tihomirov, Nov 3, 2003
    #8
  9. Valentin Tihomirov wrote:
    >
    > Thank you for your view of entity notion. Here was mine. May be
    > compiler/simulator has a third notion of entity object. Where is a supreme
    > arbiter that can tell who is right?


    The LRM of course! ;-)

    In my opinion your code is correct. I simulated your code (see below) in ModelSim.
    The output did not contain any surprise:

    bash> vsim -c 'my_ent(ext_arch)' -do 'run -a; quit'
    Reading /appl/iccadm/MTI/mti_5.7d/tcl/vsim/pref.tcl

    # 5.7d

    # vsim -do {run -a; quit} -c my_ent(ext_arch)
    # // ModelSim SE VHDL 5.7d May 2 2003 SunOS 5.8
    # //
    # // Copyright Model Technology, a Mentor Graphics Corporation company, 2003
    # // All Rights Reserved.
    # // UNPUBLISHED, LICENSED SOFTWARE.
    # // CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
    # // PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
    # //
    # Loading /appl/iccadm/MTI/mti_5.7d/bin/../sunos5/../std.standard
    # Loading work.my_ent(ext_arch)
    # Loading work.my_ent(basic_arch)
    # run -a; quit
    # ** Note: Hi, I am basic_arch
    # Time: 0 ps Iteration: 0 Instance: /my_ent/base
    # ** Note: Hi, I am ext_arch
    # Time: 0 ps Iteration: 0 Instance: /my_ent



    ENTITY my_ent IS
    END ENTITY my_ent;

    ARCHITECTURE basic_arch OF my_ent IS
    BEGIN
    hello: ASSERT false
    REPORT "Hi, I am basic_arch"
    SEVERITY note;
    END basic_arch;

    ARCHITECTURE ext_arch OF my_ent IS
    BEGIN
    hello: ASSERT false
    REPORT "Hi, I am ext_arch"
    SEVERITY note;

    base: ENTITY work.my_ent(basic_arch);
    END ext_arch;


    Paul.
    Paul Uiterlinden, Nov 3, 2003
    #9
  10. But WebPack sythesis reports

    ERROR:Xst:1609 -
    C:/projects/xilinx_bad_arch_bind/../Temp/rs232/rs232/src/my/my_ent.vhd line
    23: Entity 'my_ent' is exactly the same as instance (same ports and
    generics).

    end does not proceed. Project navigator cannot bouild hierarcy due to the
    same recursion. I can not tell about quality of Xilinx chips (have not
    anything to download yet) but SW tell for itself. A new error every day!
    Valentin Tihomirov, Nov 3, 2003
    #10
  11. Valentin Tihomirov wrote:
    > But WebPack sythesis reports
    >
    > ERROR:Xst:1609 -
    > C:/projects/xilinx_bad_arch_bind/../Temp/rs232/rs232/src/my/my_ent.vhd line
    > 23: Entity 'my_ent' is exactly the same as instance (same ports and
    > generics).
    >
    > end does not proceed. Project navigator cannot bouild hierarcy due to the
    > same recursion.


    Selecting one of two architectures requires a vhdl configuration.
    You cannot use a configuration and a direct instance at the same time.
    Some synthesis software does not support vhdl configurations in any case.
    I stand by my earlier advice.

    -- Mike Treseler
    Mike Treseler, Nov 3, 2003
    #11
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