parameters for Routability estimation and analysis during RTL stages of the design.

Discussion in 'VHDL' started by santhosh, Aug 21, 2003.

  1. santhosh

    santhosh Guest

    Hello,


    I would like to know if we can identify RTL constructs and architectures
    which can cause routability problems early in the design cycle. If there are
    some common parameters which could be identified, these could be used for
    physical feasibility studies.

    I request any one you point me to some of the earlier work carried out
    in this area.

    Thanks
    Santhosh
     
    santhosh, Aug 21, 2003
    #1
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  2. Re: parameters for Routability estimation and analysis during RTLstages of the design.

    santhosh wrote:

    > I would like to know if we can identify RTL constructs and architectures
    > which can cause routability problems early in the design cycle. If there are
    > some common parameters which could be identified, these could be used for
    > physical feasibility studies.


    The only sensitivity of routing to HDL style that I have
    seen involves initializing large registers with a global
    reset signal.

    With some devices, it is not possible to route
    a global reset signal for the purpose
    of large register initialization.
    However, if I code such an synchronously, all is well.

    Consider making a prototype of large register
    and block memory inferences.

    The most important factors for reducing risk
    have nothing to do with synthesis or routing.
    It is setting up your front end tools for
    a quick edit/compile/simulate cycle and
    setting up a cvs repository for shared files.


    -- Mike Treseler
     
    Mike Treseler, Aug 21, 2003
    #2
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