Parametrized CLA adder in VHDL

Discussion in 'VHDL' started by Bojan Jovanovic, Mar 9, 2012.

  1. Hi there,

    I need to implement Carry Look Ahead binary Adder in FPGA, by
    describing it in a parametrized way. I want to use the following
    approach:

    1. To use input signals and to make carry generate and carry propagate
    signals - G and P
    2. To use G and P and to obtain signal C
    3. To use signals C and P and to obtain the sum S and the carry out
    C_out

    Generating the signals G and P is quite simply. G=A and B; P=A xor B
    The problem is how, by using parameter N (input bit widths), to
    obtain C.
    When having C it is also easy to obtain the sum signal S.

    For N=1
    C0=G0 + P0Cin;

    For N=2
    C0=G0 + P0Cin;
    C1=G1+P1G0 + P1P0C0;

    For N=3
    C0=G0 + P0Cin;
    C1=G1+P1G0 + P1P0C0;
    C2=G2+P2G1+P2P1G0+P2P1P0C0;

    For N=4
    C0=G0 + P0Cin;
    C1=G1+P1G0 + P1P0C0;
    C2=G2+P2G1+P2P1G0+P2P1P0C0;
    C3=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0;

    And so on...

    So you can see that, depending on the number of input bits (N) I have
    different number of and circuits with the different number of inputs.

    Is there any way to describe in VHDL such a structure in parametrized
    way (using for loops), so I could only change the parameter N and
    obtain the CLA adder of preferred size?

    Thank you very much for your time and effort to answer me.

    Cheers,
    Bojan
    Bojan Jovanovic, Mar 9, 2012
    #1
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  2. On Fri, 09 Mar 2012 10:04:21 -0800, Bojan Jovanovic wrote:

    > Hi there,
    >
    > I need to implement Carry Look Ahead binary Adder in FPGA, by describing
    > it in a parametrized way.


    The first question is : why?
    Most FPGAs have highly optimised carry chains, so the CLA adder will
    probably be both larger and slower. But bearing that in mind...

    > Is there any way to describe in VHDL such a structure in parametrized
    > way (using for loops), so I could only change the parameter N and obtain
    > the CLA adder of preferred size?


    Yes.
    If you are describing it in a (sequential) process, use a for loop.
    (Probably nested loops, looking at the example)

    If you are describing it in combinatorial logic, use a for...generate
    statement (or nested generate statements)

    You probably want P and G to be bit_vectors or std_logic_vectors
    so that you can address individual bits as P(0), P(1), P(i), G(j) etc

    - Brian
    Brian Drummond, Mar 9, 2012
    #2
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  3. On Mar 9, 11:10 pm, Brian Drummond <> wrote:
    > On Fri, 09 Mar 2012 10:04:21 -0800, Bojan Jovanovic wrote:
    > > Hi there,

    >
    > > I need to implement Carry Look Ahead binary Adder in FPGA, by describing
    > > it in a parametrized way.

    >
    > The first question is : why?
    > Most FPGAs have highly optimised carry chains, so the CLA adder will
    > probably be both larger and slower. But bearing that in mind...
    >
    > > Is there any way to describe in VHDL such a structure in parametrized
    > > way (using for loops), so I could only change the parameter N and obtain
    > > the CLA adder of preferred size?

    >
    > Yes.
    > If you are describing it in a (sequential) process, use a for loop.
    > (Probably nested loops, looking at the example)
    >
    > If you are describing it in combinatorial logic, use a for...generate
    > statement (or nested generate statements)
    >
    > You probably want P and G to be bit_vectors or std_logic_vectors
    > so that you can address individual bits as P(0), P(1), P(i), G(j) etc
    >
    > - Brian


    Hi Brian,

    I know very that today's FPGA devices have fast carry propagation
    blocks. I just want to make some comparative analysis between a few
    adder architectures. One of them is a CLA adder.

    I share your opinion that by using nested loops I could implement CLA.
    However, after implementing my VHDL code I obtain the wrong results in
    the simulation.
    Please, take a look on my VHDL code and tell me do you see some
    irregularities. I will deeply and honestly appreciate your response!
    The VHDL code is following:

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;


    ENTITY cla_n IS
    GENERIC(N : NATURAL:=8);

    PORT (a,b : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
    cin: in std_logic;
    C_out:eek:ut std_logic;
    s : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0));

    END cla_n;

    architecture cla_n_arh of cla_n is
    signal carry_gen:std_logic_vector(N-1 downto 0);
    signal carry_prop:std_logic_vector(N-1 downto 0);
    signal c:std_logic_vector(N-1 downto 0);

    begin


    ---- carry_generate and carry_propagate signals
    carry_gen<=a and b;
    carry_prop<= a xor b;


    process (a,b,cin)
    variable pom1:std_logic;
    variable pom2:std_logic;
    variable pom3:std_logic;
    variable pom4:std_logic;
    variable pom5:std_logic;
    begin
    s(0)<=cin xor carry_prop(0);
    c(0)<=carry_gen(0) or (carry_prop(0)and cin);
    pom1:='0';
    pom2:='0';
    pom3:='0';
    pom4:='0';
    --pom5(0):='0';
    pom5:=cin;
    for j in 1 to N-1 loop
    pom1:=carry_gen(j);
    for i in 1 to j loop
    pom2:=carry_gen(j-i);
    for k in 1 to i loop
    pom2:=pom2 and carry_prop(j-k+1);
    end loop;
    pom3:=pom3 or pom2;
    end loop;

    for p in 0 to j loop
    pom5:=pom5 and carry_prop(p);
    end loop;

    c(j)<=pom1 or pom3 or pom5;
    s(j)<=c(j-1)xor carry_prop(j);

    end loop;
    C_out<=c(N-1);

    end process;

    end architecture cla_n_arh;
    Bojan Jovanovic, Mar 9, 2012
    #3
  4. On Fri, 09 Mar 2012 14:54:53 -0800, Bojan Jovanovic wrote:

    > On Mar 9, 11:10 pm, Brian Drummond <> wrote:
    >> On Fri, 09 Mar 2012 10:04:21 -0800, Bojan Jovanovic wrote:
    >> > Hi there,

    >>
    >> > I need to implement Carry Look Ahead binary Adder in FPGA, by
    >> > describing it in a parametrized way.

    >>
    >> The first question is : why?
    >> Most FPGAs have highly optimised carry chains, so the CLA adder will
    >> probably be both larger and slower. But bearing that in mind...
    >>
    >> > Is there any way to describe in VHDL such a structure in parametrized
    >> > way (using for loops), so I could only change the parameter N and
    >> > obtain the CLA adder of preferred size?

    >>
    >> Yes.
    >> If you are describing it in a (sequential) process, use a for loop.
    >> (Probably nested loops, looking at the example)
    >>
    >> If you are describing it in combinatorial logic, use a for...generate
    >> statement (or nested generate statements)
    >>
    >> You probably want P and G to be bit_vectors or std_logic_vectors so
    >> that you can address individual bits as P(0), P(1), P(i), G(j) etc
    >>
    >> - Brian

    >
    > Hi Brian,
    >
    > I know very that today's FPGA devices have fast carry propagation
    > blocks. I just want to make some comparative analysis between a few
    > adder architectures. One of them is a CLA adder.
    >
    > I share your opinion that by using nested loops I could implement CLA.
    > However, after implementing my VHDL code I obtain the wrong results in
    > the simulation.
    > Please, take a look on my VHDL code and tell me do you see some
    > irregularities. I will deeply and honestly appreciate your response! The
    > VHDL code is following:


    Pay attention to the sensitivity list of any combinatorial process you
    write.

    If you are new to VHDL, learn the importance of postponed assignment and
    the delta cycle model, and the semantics of assignment to a signal versus
    a variable in a process. It is quite simple and, once learned, gives
    reliable and predictable results.

    Your process uses signals that are not in its sensitivity list; that is
    the likely source of your problem.

    Incidentally, you may find the "for .. generate" form works without
    having to write an explicit process.

    - Brian
    Brian Drummond, Mar 10, 2012
    #4
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