parse error: unexpected if in xilinx ise 8.1i

Discussion in 'VHDL' started by revu, Feb 26, 2008.

  1. revu

    revu Guest

    architecture Behavioral of addsubmain is

    signal sL,sS :std_logic;
    signal eL,eS:std_logic_vector(7 downto 0);
    signal fracL,fracS:std_logic_vector(23 downto 0);

    signal sX_B : std_logic;
    signal op_X : std_logic;

    signal diff : integer;

    signal X_A : std_logic_vector(24+diff downto 0);
    signal X_B : std_logic_vector(24+diff downto 0);
    signal X_R : std_logic_vector(24+diff downto 0);

    begin
    sX_B <= oper xor s_B;

    if exp_A < exp_B then
    eS <= exp_A;
    fracS <= frac_A;
    sS <= s_A;
    eL <= exp_B;
    fracL <= frac_B;
    sL <= sX_B;
    elsif exp_B < exp_A then
    eS <= exp_B;
    fracS <= frac_B;
    sS <= sX_B;
    eL <= exp_A;
    fracL <= frac_A;
    sL <= s_A;
    end if;
    my code goes like this.. exp_A and exp_B have been declared as
    std_logic_vectors of same size in the entity.
    the xilinx ise tool shows "parse error: unexpected if" at the beginning of
    this part of code, then "parse error: unexpected else" and also "error:
    unexpected if, semicolon expected" at the line of end if.
    i can't proceed without getting this conditional statement corrected. i
    even tried using case instead of if.. but tat too is erroneous...

    wat is wrong with my code?

    --
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    revu, Feb 26, 2008
    #1
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  2. revu wrote:

    > architecture Behavioral of addsubmain is
    >
    > signal sL,sS :std_logic;
    > signal eL,eS:std_logic_vector(7 downto 0);
    > signal fracL,fracS:std_logic_vector(23 downto 0);
    >
    > signal sX_B : std_logic;
    > signal op_X : std_logic;
    >
    > signal diff : integer;
    >
    > signal X_A : std_logic_vector(24+diff downto 0);
    > signal X_B : std_logic_vector(24+diff downto 0);
    > signal X_R : std_logic_vector(24+diff downto 0);
    >
    > begin
    > sX_B <= oper xor s_B;
    >
    > if exp_A < exp_B then
    > eS <= exp_A;
    > fracS <= frac_A;
    > sS <= s_A;
    > eL <= exp_B;
    > fracL <= frac_B;
    > sL <= sX_B;
    > elsif exp_B < exp_A then
    > eS <= exp_B;
    > fracS <= frac_B;
    > sS <= sX_B;
    > eL <= exp_A;
    > fracL <= frac_A;
    > sL <= s_A;
    > end if;
    > my code goes like this.. exp_A and exp_B have been declared as
    > std_logic_vectors of same size in the entity.
    > the xilinx ise tool shows "parse error: unexpected if" at the beginning of
    > this part of code, then "parse error: unexpected else" and also "error:
    > unexpected if, semicolon expected" at the line of end if.
    > i can't proceed without getting this conditional statement corrected. i
    > even tried using case instead of if.. but tat too is erroneous...
    >
    > wat is wrong with my code?


    You can't use 'if' as a concurrent statement (i.e. outside a process). 'if'
    is a sequential statement, so it can only be used in sequential areas, such
    as processes, procedures and functions.

    So I would suggest putting your stuff in a process.

    Also, your signals are not assigned unconditionally, so you will create
    latches. Add an else, or assign default values before the if.

    ab_cmb: process(exp_A, exp_B, frac_A, frac_B, s_A, sX_B, exp_B) is
    begin
    if exp_A < exp_B then
    eS <= exp_A;
    fracS <= frac_A;
    sS <= s_A;
    eL <= exp_B;
    fracL <= frac_B;
    sL <= sX_B;
    elsif exp_B < exp_A then
    eS <= exp_B;
    fracS <= frac_B;
    sS <= sX_B;
    eL <= exp_A;
    fracL <= frac_A;
    sL <= s_A;
    else -- exp_A equals exp_B
    eS <= ...;
    fracS <= ...;
    sS <= ...;
    eL <= ...;
    fracL <= ...;
    sL <= ...;
    end if;
    end process ab_cmb;

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, Feb 26, 2008
    #2
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  3. revu wrote:
    > architecture Behavioral of addsubmain is

    ....

    > signal diff : integer;
    >
    > signal X_A : std_logic_vector(24+diff downto 0);

    ....
    Is the above legal? You seem to have the width of X_A depend on the
    value of diff? For that to work, diff would need to be a constant
    (possibly a generic)?
    David R Brooks, Feb 26, 2008
    #3
  4. revu

    revu Guest

    revu, Feb 27, 2008
    #4
  5. revu wrote:

    > so is it legal if i declare the signal X_A after calculating diff ie,
    > after 'begin' of the architecture??


    No, because after the 'begin' of an architecture you cannot declare signals.

    The width of a signal is static (cannot change during simulation). So in the
    declaration of a signal, its width can only be derived from constants and
    generics. Not from the value of another signal or variable.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
    Paul Uiterlinden, Feb 27, 2008
    #5
  6. revu

    revu Guest

    revu, Mar 3, 2008
    #6
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