parse error, unexpected IF

[Frank Buss]

The following code works in Xilinx ISE 8.1:

adds: for i in 0 to bits - 1 generate
add(i) <= shift_add(i, bits, a) when b(i) = '1'
else to_unsigned(0, 2 * bits - 1);
end generate;

with this function definition (I need this complicated function, because
to_unsigned doesn't allow to generate 0 bits and I didn't found another
function) :

function shift_add(shift: integer; bits: integer; b: unsigned)
return unsigned is
variable result: unsigned(2 * bits - 1 downto 0);
begin
if shift < bits then
for i in 0 to bits - shift - 1 loop
result(2 * bits - 1 - i) := '0';
end loop;
end if;
for i in 0 to bits - 1 loop
result(i + shift) := b(i);
end loop;
if shift > 0 then
for i in 0 to shift - 1 loop
result(i) := '0';
end loop;
end if;
return result;
end shift_add;

If I want to inline the function, it doesn't work. Even a simple "if"
doesn't work:

adds: for i in 0 to bits - 1 generate
if i > 0 then
add(i) <= b"00000000";
end if;
end generate;

For this code I get the error "parse error, unexpected IF". Is there a bug
in my code or in ISE?

 

[Andy Peters]

If I want to inline the function, it doesn't work. Even a simple "if"
doesn't work:

adds: for i in 0 to bits - 1 generate
if i > 0 then
add(i) <= b"00000000";
end if;
end generate;

For this code I get the error "parse error, unexpected IF". Is there a bug
in my code or in ISE?

In the generate loop, the "if" is a generate conditional and not logic,
and as such the parser is confused. In other words, it expects an "if
.... generate" construct, and I suspect the error you're getting is at
the "end if" (it wants to see "end generate").

-a

 

[Frank Buss]

In the generate loop, the "if" is a generate conditional and not logic,
and as such the parser is confused. In other words, it expects an "if
... generate" construct, and I suspect the error you're getting is at
the "end if" (it wants to see "end generate").

Thanks, this was the bug. When I use the "if...generate" construct inside
the loop, it works. But why makes VHDL things more complicated than
necessary and doesn't allow the same code in functions and outside of
functions?

For my special case (see asynchronous VHDL example thread) I was able to
delete the conditional and the function completely:

add(0) <= to_unsigned(0, bits) & a when b(0) = '1'
else to_unsigned(0, 2 * bits);
adds: for i in 1 to bits - 1 generate
add(i) <= to_unsigned(0, bits - i) & a & to_unsigned(0, i)
when b(i) = '1'
else to_unsigned(0, 2 * bits);
end generate;

It was really fascinating after uploading it to my Spartan-3 starter kit
and watching the LEDs when switching the switches

 

[Andy]

For-generate and for-loops are different animals altogether:

For-generate contains only concurrent statements.
For-generate requires a static loop index constraint.

For-loops contain only sequential statements.
For loops can have dynamic loop index constraints.
For loops can have exit statements.

For synthesis, both get treated similarly (unrolled).

Because they are not the same, they have different syntaxes.

Andy