parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK

Discussion in 'VHDL' started by krishlal925, May 22, 2007.

  1. krishlal925

    krishlal925

    Joined:
    May 22, 2007
    Messages:
    1
    i got that error on the line after begin check it out:


    signal C : std_logic_vector(3 downto 0);

    begin
    halfadder port map(A(0), B(0), S(0), c => C(0));
    fulladder port map(A(1), B(1), C(0), S(1), Cout => C(1));
    fulladder port map(A(2), B(2), C(1), S(2), Cout => C(2));
    fulladder port map(A(3), B(3), C(2), S(3), Cout => Cout);
    end Behavioral;

    any suggestions?
    krishlal925, May 22, 2007
    #1
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  2. krishlal925

    jaga

    Joined:
    Mar 31, 2011
    Messages:
    2
    hi

    can u please define A B C an all...
    jaga, Mar 31, 2011
    #2
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  3. krishlal925

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    you must add a label to each instance, like:
    Code:
    begin
    ha: halfadder port map(A(0), B(0), S(0), c => C(0));
    fa1: fulladder port map(A(1), B(1), C(0), S(1), Cout => C(1));
    fa2: fulladder port map(A(2), B(2), C(1), S(2), Cout => C(2));
    fa3: fulladder port map(A(3), B(3), C(2), S(3), Cout => Cout);
    end Behavioral;
    
    joris, Apr 1, 2011
    #3
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