Parser to convert a state machine written in VHDL to .dot format readable by graphviz

Discussion in 'VHDL' started by reuven, Jul 27, 2006.

  1. reuven

    reuven Guest

    Hi,

    Does anyone know of a parser that can convert a state machine written
    in VHDL to the .dot format ?
     
    reuven, Jul 27, 2006
    #1
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  2. Re: Parser to convert a state machine written in VHDL to .dot formatreadable by graphviz

    reuven wrote:

    > Does anyone know of a parser that can convert a state machine written
    > in VHDL to the .dot format ?


    Might be an interesting project.
    However, the quartus state machine viewer
    has already solved this problem.
    It picks state machines out of vhdl or verilog
    code and can print them like this:

    http://home.comcast.net/~mike_treseler/pseudo_states.pdf

    -- Mike Treseler
     
    Mike Treseler, Jul 27, 2006
    #2
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