parser VHDL to DOT (graphviz)

Discussion in 'VHDL' started by amamory@gmail.com, Dec 19, 2006.

  1. Guest

    Hi,

    I am looking for a parser to translate VHDL to DOT (graphviz).
    I want to automaticaly create figures for FSMs and hierarquical
    representation of modules.

    Does anyone know some starting points ?

    regards,
    Alexandre
    , Dec 19, 2006
    #1
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  2. wrote:

    > I am looking for a parser to translate VHDL to DOT (graphviz).


    The quartus state machine viewer
    can pick directed graphs out of vhdl or verilog
    code and can print them like this:

    http://home.comcast.net/~mike_treseler/pseudo_states.pdf

    It is unlikely that a vhdl user would
    reinvent this wheel.

    -- Mike Treseler
    Mike Treseler, Dec 19, 2006
    #2
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  3. Guest

    Mike Treseler escreveu:

    > wrote:
    >
    > > I am looking for a parser to translate VHDL to DOT (graphviz).

    >
    > The quartus state machine viewer
    > can pick directed graphs out of vhdl or verilog
    > code and can print them like this:
    >
    > http://home.comcast.net/~mike_treseler/pseudo_states.pdf
    >
    > It is unlikely that a vhdl user would
    > reinvent this wheel.
    >
    > -- Mike Treseler


    I forgot to mention that it must be a command-line program. I want to
    build an "automatic
    documentation environment" where the tool generates a latex doc with
    things like ports, hierarchy, graphical fsm, etc

    something like :
    - vhdldoc test.vhd > test.tex
    - pdflatex test.tex

    but i need a parser to generate the figures related to FSM and
    hierarchy.

    Dear Mike,
    when you say "quartus" you mean Altera's software ?

    Alexandre
    , Dec 19, 2006
    #3
  4. Guest

    escreveu:

    > Mike Treseler escreveu:
    >
    > > wrote:
    > >
    > > > I am looking for a parser to translate VHDL to DOT (graphviz).

    > >
    > > The quartus state machine viewer
    > > can pick directed graphs out of vhdl or verilog
    > > code and can print them like this:
    > >
    > > http://home.comcast.net/~mike_treseler/pseudo_states.pdf
    > >
    > > It is unlikely that a vhdl user would
    > > reinvent this wheel.
    > >
    > > -- Mike Treseler

    >
    > I forgot to mention that it must be a command-line program. I want to
    > build an "automatic
    > documentation environment" where the tool generates a latex doc with
    > things like ports, hierarchy, graphical fsm, etc
    >
    > something like :
    > - vhdldoc test.vhd > test.tex
    > - pdflatex test.tex
    >
    > but i need a parser to generate the figures related to FSM and
    > hierarchy.
    >
    > Dear Mike,
    > when you say "quartus" you mean Altera's software ?
    >
    > Alexandre


    Moreover, a solution based on free software and/or free libraries
    would be better :)

    Alexandre
    , Dec 19, 2006
    #4
  5. wrote:

    >> I forgot to mention that it must be a command-line program. I want to
    >> build an "automatic
    >> documentation environment" where the tool generates a latex doc with
    >> things like ports, hierarchy, graphical fsm, etc
    >> something like :
    >> - vhdldoc test.vhd > test.tex
    >> - pdflatex test.tex
    >> but i need a parser to generate the figures related to FSM and
    >> hierarchy.



    Similar tools exist, but no open
    source code as far as I know.

    Who is the audience?
    I would learn more from a working testbench
    than a binder full of such documents.

    >> when you say "quartus" you mean Altera's software ?


    Yes. A licensed copy gives you an interactive
    viewer with hierarchical blocks that covers
    your requirements except for the command line.
    The emacs vhdl-mode speedbar *is* open source
    but covers only structure.

    -- Mike Treseler
    Mike Treseler, Dec 19, 2006
    #5
  6. Amal Guest

    Amal, Jan 2, 2007
    #6
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