parser VHDL to DOT (graphviz)

[amamory]

Hi,

I am looking for a parser to translate VHDL to DOT (graphviz).
I want to automaticaly create figures for FSMs and hierarquical
representation of modules.

Does anyone know some starting points ?

regards,
Alexandre

 

[Mike Treseler]

I am looking for a parser to translate VHDL to DOT (graphviz).

The quartus state machine viewer
can pick directed graphs out of vhdl or verilog
code and can print them like this:

http://home.comcast.net/~mike_treseler/pseudo_states.pdf

It is unlikely that a vhdl user would
reinvent this wheel.

-- Mike Treseler

 

[amamory]

Mike Treseler escreveu:

The quartus state machine viewer
can pick directed graphs out of vhdl or verilog
code and can print them like this:

http://home.comcast.net/~mike_treseler/pseudo_states.pdf

It is unlikely that a vhdl user would
reinvent this wheel.

-- Mike Treseler

I forgot to mention that it must be a command-line program. I want to
build an "automatic
documentation environment" where the tool generates a latex doc with
things like ports, hierarchy, graphical fsm, etc

something like :
- vhdldoc test.vhd > test.tex
- pdflatex test.tex

but i need a parser to generate the figures related to FSM and
hierarchy.

Dear Mike,
when you say "quartus" you mean Altera's software ?

Alexandre

 

[amamory]

(e-mail address removed) escreveu:

Mike Treseler escreveu:


I forgot to mention that it must be a command-line program. I want to
build an "automatic
documentation environment" where the tool generates a latex doc with
things like ports, hierarchy, graphical fsm, etc

something like :
- vhdldoc test.vhd > test.tex
- pdflatex test.tex

but i need a parser to generate the figures related to FSM and
hierarchy.

Dear Mike,
when you say "quartus" you mean Altera's software ?

Alexandre

Moreover, a solution based on free software and/or free libraries
would be better

Alexandre

 

[Mike Treseler]

Similar tools exist, but no open
source code as far as I know.

Who is the audience?
I would learn more from a working testbench
than a binder full of such documents.

Yes. A licensed copy gives you an interactive
viewer with hierarchical blocks that covers
your requirements except for the command line.
The emacs vhdl-mode speedbar *is* open source
but covers only structure.

-- Mike Treseler

 

[Amal]

Moreover, a solution based on free software and/or free libraries
would be better

Alexandre

There is a VHDL documentation tool that parses VHDL files using PERL.
You can take a look at it here:

http://schwick.web.cern.ch/schwick/vhdldoc/

It can create HTM or even LATEX I think.

Or I you can use ANTLR (http://www.antlr.org) and the VHDL grammar
(http://www.antlr.org/grammar/1086696923011/vhdlams/index.html) to
create your own parser.

-- Amal