parsing a subtype_indication

Discussion in 'VHDL' started by Ole Nielsby, Dec 12, 2007.

  1. Ole Nielsby

    Ole Nielsby Guest

    Given this lump:


    entity my_entity is
    port
    (
    my_vector : out my_vector_type(17 downto 0)
    );
    end my_entity;


    it is clear that
    my_vector_type(17 downto 0)
    parses as:
    subtype_indication
    type_mark
    type_name or subtype_name
    simple_name
    identifier "my_vector_type"
    constraint
    index_constraint
    "("
    discrete_range
    range
    simple_expression "17"
    direction "downto"
    simple_expression "0"
    ")"

    What I'd like to know is, when the parser has seen:
    my_vector_type(
    can it, without symbol table information, infer that
    the type_mark has ended and a constraint has begun?

    Or can a type_name start with xxx( ?
    The BNF grammar seems to allow this, allowing a
    name to be a function call, but I am having a hard time
    trying to find out if it is a real possibility or just lax
    grammar spec.
     
    Ole Nielsby, Dec 12, 2007
    #1
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  2. Ole Nielsby wrote:

    > What I'd like to know is, when the parser has seen:
    > my_vector_type(
    > can it, without symbol table information, infer that
    > the type_mark has ended and a constraint has begun?


    Don't know, but "my_vector_type(17 downto 0)"
    is a *subtype* of some anonymous unconstrained array type
    unless it is explicitly declared.

    -- Mike Treseler
     
    Mike Treseler, Dec 12, 2007
    #2
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  3. Ole Nielsby

    Guest

    On Dec 12, 5:28 am, "Ole Nielsby" <ole.niel...@tekare-you-
    spamminglogisk.dk> wrote:
    >
    > What I'd like to know is, when the parser has seen:
    > my_vector_type(
    > can it, without symbol table information, infer that
    > the type_mark has ended and a constraint has begun?
    >


    In the general BNF grammar, no, because type_mark is a name, which
    might be a slice name, which can also contain a (17 downto 0). So you
    need to use a special production for type mark which allows only an
    expanded name. I've found it easier to use parser combinators to
    build a number of abstract parse trees, then resolve each, using
    symbol table info, to a (possibly empty) concrete interpretation, then
    check that the set of abstract trees yields only one valid
    interpretation. You can trade off the number of parse tree branches
    for the richness of your AST.

    You're going to have a really hard time if you try to build a
    "conventional" compiler for VHDL, employing syntax-directed
    translation driven by the symtab.

    - Kenn
     
    , Dec 14, 2007
    #3
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