partial aggregate assignment?

Discussion in 'VHDL' started by jens, Oct 6, 2005.

  1. jens

    jens Guest

    Hi,

    I'm trying to do a partial aggregate assigment, this fragmented
    pseudo-code shows what I'm trying to do... (INDEX1 and INDEX2 are
    constants between 0 and 31)

    signal test_vector: std_logic_vector(31 downto 0);

    test_vector <= (INDEX1 => open, INDEX2 => open, others => '1');

    process1...
    test_vector(INDEX1) <= {logic};
    end process;

    process2...
    test_vector(INDEX2) <= {logic};
    end process;

    I'm trying to assign most of the vector to '1' and have two separate
    processes assign the remaining two bits. The compiler doesn't like
    "open" or "null", and any other assignment wouldn't resolve correctly
    ('-' resolves to 'X', 'U' resolves to 'U', I'm trying to avoid 'Z'
    because the code should work with any FPGA). On the other hand, maybe
    'Z' is the answer and the FPGA compiler will be smart enough to not
    implement a tri-state signal in an architecture that doesn't support
    internal tri-states. I'm currently using an Altera Stratix FPGA but it
    needs to be portable to any other vendor.

    Another option is to combine the two processes into one and use a
    default assignment for the whole vector, but I'm trying to avoid
    changing more than I need to (I inherited the design). I suppose
    another option is to use a loop and only assign certain elements, or
    use three assigment statements like:

    test_vector(INDEX1-1 downto 0) <= (others => '1');
    test_vector(INDEX2-1 downto INDEX1+1) <= (others => '1');
    test_vector(31 downto INDEX2+1) <= (others => '1');

    But that makes some assumptions about the values of INDEX1 and INDEX2
    and can get kind of convoluted, especially if INDEX3 needs to be added
    later.

    It seems like there should be an easier and more elegant way.

    Thanks in advance for any advice...
     
    jens, Oct 6, 2005
    #1
    1. Advertising

  2. jens wrote:

    > I'm trying to assign most of the vector to '1' and have two separate
    > processes assign the remaining two bits.


    Your choices are combine the processes or split the signal.

    > I'm trying to avoid
    > changing more than I need to (I inherited the design).


    It's yours now.


    -- Mike Treseler
     
    Mike Treseler, Oct 6, 2005
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Billy
    Replies:
    2
    Views:
    524
    Billy
    Feb 1, 2006
  2. Paul B

    Partial Aggregate Assignment

    Paul B, Dec 7, 2006, in forum: VHDL
    Replies:
    4
    Views:
    591
    Paul Uiterlinden
    Dec 10, 2006
  3. Thomas Heller
    Replies:
    13
    Views:
    887
    Michele Simionato
    Feb 8, 2007
  4. J. Clifford Dyer

    Re: Partial 1.0 - Partial classes for Python

    J. Clifford Dyer, Feb 8, 2007, in forum: Python
    Replies:
    0
    Views:
    536
    J. Clifford Dyer
    Feb 8, 2007
  5. Sudoer
    Replies:
    12
    Views:
    1,367
    Jonathan Bromley
    Jul 30, 2011
Loading...

Share This Page