pass value from system verilog to VHDL (std_logic_vector)

Discussion in 'VHDL' started by sundar, Nov 12, 2007.

  1. sundar

    sundar Guest

    Hi,
    In my VHDL DUT I have a generic declared as std_logic_vector as below
    generic_name : std_logic_vector := "0100000000";

    My verification environment is in System Verilog where I need to pass
    a value to this generic during mapping it in System Verilog

    dut
    #(
    ..generic_name (),
    )
    ....
    I cudnt able to pass any value from my test bench and my Questasim
    6.3c simulator states
    # ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
    for the associated Verilog parameter.

    Please let me know your thoughts.

    Thanks,
    Sundar
    Note: I had a workaround by leaving the dut mapping as blank and
    passing value during vsim like
    -g/tb/dut_0/generic_name=10'b0100000000.
    sundar, Nov 12, 2007
    #1
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  2. sundar <> writes:
    > I cudnt able to pass any value from my test bench and my Questasim
    > 6.3c simulator states
    > # ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
    > for the associated Verilog parameter.


    See section "VHDL Instantiation Criteria Within Verilog" in the Questa
    User Guide. std_logic_vector is not among the supported types for
    generics.

    Regards
    Marcus

    --
    note that "property" can also be used as syntaxtic sugar to reference
    a property, breaking the clean design of verilog; [...]

    (seen on http://www.veripool.com/verilog-mode_news.html)
    Marcus Harnisch, Nov 12, 2007
    #2
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  3. sundar

    sundar Guest

    On Nov 12, 6:36 pm, Marcus Harnisch <> wrote:
    > sundar <> writes:
    > > I cudnt able topassany value from my test bench and my Questasim
    > > 6.3c simulator states
    > > # ** Error: (vsim-3051) VHDL generic 'generic_name' is the wrong type
    > > for the associated Verilog parameter.

    >
    > See section "VHDL Instantiation Criteria Within Verilog" in the Questa
    > User Guide. std_logic_vector is not among the supported types for
    > generics.
    >
    > Regards
    > Marcus
    >
    > --
    > note that "property" can also be used as syntaxtic sugar to reference
    > a property, breaking the clean design of verilog; [...]
    >
    > (seen onhttp://www.veripool.com/verilog-mode_news.html)

    Hello Marcus,
    I decalred parameter inteeger type and passed it to VHDL wrapper to
    convert it into std_logic_vector which helped me in this regard.

    Thanks,
    Sundar
    sundar, Nov 27, 2007
    #3
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