Passing complex unconstrained array as signal to a procedure

[Anne Onime]

I have the following definitions in a VHDL architecture:

TYPE MemType IS ARRAY (MemDepth-1 DOWNTO 0) OF std_ulogic_vector(DataWidth-1 DOWNTO 0);
SIGNAL Mem : MemType := (OTHERS => (OTHERS => '0'));

such that MemDepth and DataWidth are generics on the entity. I would like to create the procedure "InitMem" in a
package to initialize the Mem signal to a specific pattern. But I do not know what the specific settings of
MemDepth and DataWidth will be for each instance of the entity that will be calling the procedure. So I would
ideally like to specify an unconstrained parameter for the procedure. Obviously, I can also pass the MemDepth and
DataWidth values along with the signal itself so that the procedure knows the array bounds.

Is this possible? If so, what would the procedure look like? I would have thought it would be something like this,
but I am getting compiler errors that I cannot define an unconstrained type:

PACKAGE InitPkg IS

TYPE MemType IS ARRAY (natural RANGE <>) OF std_ulogic_vector;

PROCEDURE InitMem (
SIGNAL Mem : INOUT MemType;
CONSTANT DataWidth : IN positive;
CONSTANT MemDepth : IN positive) IS

...

Note that this initialization is NOT intended to be synthesizable. Any suggestions?

- vhannak

 

[Tricky]

It should be possible with the new VHDL2008 standard, but its not very
well supported yet. Until then, the only thing you can do is to
constrain the std_ulogic_vector.

 

[Paul Uiterlinden]

I have the following definitions in a VHDL architecture:

TYPE MemType IS ARRAY (MemDepth-1 DOWNTO 0) OF
std_ulogic_vector(DataWidth-1 DOWNTO 0);

SIGNAL Mem : MemType := (OTHERS => (OTHERS => '0'));

Yuck: signal+memory.

If the memory is going to contain more than a fair amount of bits, use a
variable instead of a signal. A signal consumes about 100X more memory on
your workstation/PC then a variable would.

So if at all possible, keep mem confined to a single process, so it can be a
variable. Limiting the number of processes (preferably: 1) is a good idea
anyway.

And indeed as said by Tricky, only VHDL-2008 supports arrays of
unconstrained vectors.

 

[KJ]

I have the following definitions in a VHDL architecture:

  TYPE   MemType IS ARRAY (MemDepth-1 DOWNTO 0) OF std_ulogic_vector(DataWidth-1 DOWNTO 0);
  SIGNAL Mem : MemType := (OTHERS => (OTHERS => '0'));

such that MemDepth and DataWidth are generics on the entity.  I would like to create the procedure "InitMem" in a
package to initialize the Mem signal to a specific pattern.  But I do not know what the specific settings of
MemDepth and DataWidth will be for each instance of the entity that will be calling the procedure.

Note that this initialization is NOT intended to be synthesizable.  Any suggestions?

Use two dimensional arrays instead for the procedure. Then you can
either:
- Change the entity (and whatever instantiates the entity...) to use
2d arrays...probably more work than it's worth or...
- Create functions within the architecture of the entity to convert
your array of arrays into a 2d array. It's not that difficult to do.

Kevin Jennings

 

[Charles Gardiner]

Hi Anne,

you are allowed just one "degree of freedom" with VHDL before 2008. I regularily
have things like the following in my testbenches:


subtype t_slv32 is std_logic_vector(31 downto 0);
type t_tlm_payload is array (natural range <>) of t_slv32;

procedure memwr( addr : in std_logic_vector;
pload : in t_tlm_payload;
signal clk : in std_logic;
.....

and then call the procedure with
memwr(X"1234001C",
(X"96699669", X"1E711E71"),
clk, ....

If you use a generic for the word size you can probably still implmenet a portable
/reusable concept, depending on your application.