PCI plug n play and Graphics card implementation

[mansoor.naseer]

Hello all,

Can someone please answer the following questions?

1. I am using a VGA graphics core with 60Hz refresh rate and 640x480
pixels (24bit), requiring about 25MHz xtal. The FPGA development board
comes equipped with that, the problem is how to provide a fast pixel
access. The SDRAM connected has an access time of 15ns, if I could just
come up with some method to update the SRAM contents very quickly, i
can display moving graphics onto the monitor using FPGA? Are there any
simple graphic chips which can do this job for custom display designs
without using the processors?

2. The second question indirectly relates to the PCI, however, before
that, can someone please tell me exactly how plug and play works? When
the computer boots what steps are taken and how the system determine
how many legal devices are connected to the pci.

3. The base address register, it is not hardwired but assigned on the
fly? I have problems understanding the configuration step in the pci
core. Any comments for a starter?

Thanks in advance

Mak

 

[DerekSimmons]

I'm responding to your first question about moving graphics.

What development board are you using? And how much memory is available
and how is it organized?

By moving graphics, do you mean 2D or 3D graphics?

You have two choices: just in time rendering implementation or a double
buffered display. The just in time rendering display doesn't require as
much memory and it works great for text and simple 2D graphics. An
example of this is the older arcade games (Pac Man, Space Invaders,
Atari 2600). A double buffer display is memory hungry and it is used by
the 3D cards of today.

Which method are you intending on using?

Derek

 

[DerekSimmons]

When you say VGA what do you exactly mean? VGA was an implementation of
a graphics adapter made by IBM. It became the standard for PCs because
other venders picked it up and supported it on the PC.

Are you trying to create an implementation of a VGA card or are you
trying to create display card for displaying images from a PC using the
PCI bus?

Derek

 

[Jason Zheng]

2. The second question indirectly relates to the PCI, however, before
that, can someone please tell me exactly how plug and play works? When
the computer boots what steps are taken and how the system determine
how many legal devices are connected to the pci.

During the configuration phase of the PCI, the kernel probes the PCI bus
for any PCI devices using the PCI configuration commands. If a device is
found, the following steps are taken:

1. Find out how much address space the device needs for each base address.
2. Allocate the address space within the kernel, usually by updating
some address table.
3. Tell the PCI device to use address xxxx for base address y

During the configuration phase, obviously you can't address the PCI
device with the I/O space or memory space address. You use the device
number, bus number, function number, and register number to address. The
PCI host chip then asserts corresponding the IDSEL pin of the PCI device
to notify that it is being configured.

hth,

jz

 

[Mak]

Thank you for the response,

I am making a simple 640x480 24bit graphics card which can be updated
through the PCI bus. The core reads the current pixel to display using
the contents from the onboard SRAM. I am using AVNET's S3-1500
demonstration board with onboard Cypress SRAM 1MB (32bit). It also
resides an ADV7123 Triple Video DAC converter for video display (RGB-
8 bits each).

I only need to update a 2D image on the screen which will only display
text images not moving graphics, for instance a simple touch screen
menu.

Whats double buffering? Is it more suitable for the current
application. Also cant i just use the serial port for updating the
contents of SRAM since its just a text image? Furthermore, what might
happen if I try writing to a specific address while the graphics core
is access it for reading?

Thanks

 

[DerekSimmons]

In the next couple of weeks I'm putting the finishing touches on a
triangle rasterization library. My development platform is a Stratix II
EDK/SDK. I'll also be posting it to the NIOS II forum website when
finished. I was wondering if you were interested and if there was any
other interest.

Thanks,
Derek

 

[Andy Peters]

2. The second question indirectly relates to the PCI, however, before
that, can someone please tell me exactly how plug and play works? When
the computer boots what steps are taken and how the system determine
how many legal devices are connected to the pci.

This is too big a subject for a newsgroup posting. You should pick up
the Mindshare PCI book. When you've finished reading that telephone
book, you'll have a good idea what goes on.

3. The base address register, it is not hardwired but assigned on the
fly? I have problems understanding the configuration step in the pci
core. Any comments for a starter?

First, buy that book.

Second, the base address register is assigned by the host during
enumeration. The host reads each BAR, which you must preload with a
mask that indicates the size of the required space. This mask is
simply 1s in the significant bits, so for example setting the BAR to
0xFFFF0000 would request a 64k space (the four LSBs indicate the type
of space/etc). If the host decides it can support that BAR, it writes
a valid base address to the BAR (overwriting the mask).

-a