PCI wishbone can bus

Discussion in 'VHDL' started by mungam, Mar 10, 2006.

  1. mungam

    mungam Guest

    Hello,

    I have a can ip core in verilog, I'm willing to implement it on a fpga
    PCI board. To do that I have to make a "PCI wishbone" but I don't know
    it what it consists exactly and how to do it. I have seen some articles
    about that on opencores.org but my english is poor and I'm a little bit
    newbie.
    So if anyone could help on that it would be great.
    Thank you

    Adrien Bureau
     
    mungam, Mar 10, 2006
    #1
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  2. mungam wrote:

    > I have a can ip core in verilog, I'm willing to implement it on a
    > fpga PCI board. To do that I have to make a "PCI wishbone" but I
    > don't know it what it consists exactly and how to do it. I have seen
    > some articles about that on opencores.org but my english is poor and
    > I'm a little bit newbie. So if anyone could help on that it would be
    > great. Thank you


    You need to download the PCI core from opencores. It has a Wishbone
    back-end on it which you can connect directly to your can core.

    Regards,
    Mark
     
    Mark McDougall, Mar 12, 2006
    #2
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