Perhaps a newbie question...

Discussion in 'VHDL' started by Klaus Kleiner, Dec 22, 2003.

  1. Hello

    I have a Dual Field Adder Entity, which is controlled by the control signal
    fsel: If fsel is high the the
    cout port is always 0 the adder performs a XOR operation, else this Adder
    performs a normal addition with carry and sum.
    Now i have the following problem: I have got 1 bit control signal for the
    fsel. But i have to combine this 1
    bit signal with a 32 bit input with a nand operation. How can i do this in
    VHDL? Because for a logic operation as nand both operands need to be the
    same length. Is there a trick? hope someone can give me a hint

    Thanks a lot

    library ieee;
    use ieee.std_logic_1164.all;

    entity dual_adder is
    port (cin: in std_ulogic_vector(31 downto 0);
    sin: in std_ulogic_vector(31 downto 0);
    pin: in std_ulogic_vector(31 downto 0);
    fsel: in std_ulogic;
    cout: out std_ulogic_vector(31 downto 0);
    sout: out std_ulogic_vector(31 downto 0)
    );
    end dual_adder;

    architecture structural of dual_adder is
    signal cinout : std_ulogic_vector(31 downto 0);
    signal sinout : std_ulogic_vector(31 downto 0);
    signal pinout : std_ulogic_vector(31 downto 0);
    signal orout : std_ulogic_vector(31 downto 0);

    begin
    cinout <= not (cin and sin and fsel);
    sinout <= cin xnor sin;
    pinout <= pin nand
    --!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    orout <= cinout or pinout;
    cout <= orout nand cinout;
    sout <= pin xnor sinout;
    end structural;
     
    Klaus Kleiner, Dec 22, 2003
    #1
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  2. On Mon, 22 Dec 2003 11:16:32 +0100, "Klaus Kleiner"
    <> wrote:

    >Hello
    >
    >I have a Dual Field Adder Entity, which is controlled by the control signal
    >fsel: If fsel is high the the
    >cout port is always 0 the adder performs a XOR operation, else this Adder
    >performs a normal addition with carry and sum.
    >Now i have the following problem: I have got 1 bit control signal for the
    >fsel. But i have to combine this 1
    >bit signal with a 32 bit input with a nand operation. How can i do this in
    >VHDL? Because for a logic operation as nand both operands need to be the
    >same length. Is there a trick? hope someone can give me a hint



    foo <= not bar when fsel = '1' else (others => '1');

    It's not quite nand (think about what happens when fsel is 'X') but I
    think it probably does what you want.

    Regards,
    Allan.
     
    Allan Herriman, Dec 22, 2003
    #2
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  3. "Klaus Kleiner" <> schreef in bericht
    news:bs6g86$a490g$-berlin.de...
    > Hello
    >
    > I have a Dual Field Adder Entity, which is controlled by the control

    signal
    > fsel: If fsel is high the the
    > cout port is always 0 the adder performs a XOR operation, else this Adder
    > performs a normal addition with carry and sum.
    > Now i have the following problem: I have got 1 bit control signal for the
    > fsel. But i have to combine this 1
    > bit signal with a 32 bit input with a nand operation. How can i do this in
    > VHDL? Because for a logic operation as nand both operands need to be the
    > same length. Is there a trick? hope someone can give me a hint


    I added 4 possible solutions (functions included in a test environment).

    Egbert Molenkamp


    ENTITY and_bus_with_bit IS
    GENERIC (buswidth : natural := 4);
    PORT ( ibit : IN bit;
    ibus : IN bit_vector(buswidth-1 DOWNTO 0);
    obus : OUT bit_vector(buswidth-1 DOWNTO 0));
    END and_bus_with_bit;

    ARCHITECTURE demo1 OF and_bus_with_bit IS
    FUNCTION "and" (l : IN bit; r : IN bit_vector)
    RETURN bit_vector IS
    VARIABLE res : bit_vector(r'RANGE);
    BEGIN
    FOR i IN r'RANGE LOOP
    res(i) := l AND r(i);
    END LOOP;
    RETURN res;
    END "and";

    FUNCTION "and" (l : IN bit_vector; r : IN bit)
    RETURN bit_vector IS
    BEGIN
    RETURN r and l;
    END "and";

    BEGIN
    obus <= ibus AND ibit;
    END demo1;

    ARCHITECTURE demo2 OF and_bus_with_bit IS
    FUNCTION "and" (l : IN bit; r : IN bit_vector)
    RETURN bit_vector IS
    CONSTANT lvec : bit_vector(r'RANGE) := (OTHERS => l);
    BEGIN
    RETURN lvec AND r;
    END "and";

    FUNCTION "and" (l : IN bit_vector; r : IN bit)
    RETURN bit_vector IS
    BEGIN
    RETURN r and l;
    END "and";

    BEGIN
    obus <= ibus AND ibit;
    END demo2;


    ARCHITECTURE demo3 OF and_bus_with_bit IS
    FUNCTION "and" (l : IN bit; r : IN bit_vector)
    RETURN bit_vector IS
    CONSTANT nul_vector : bit_vector(r'RANGE) := (OTHERS => '0');
    BEGIN
    IF l ='1'
    THEN RETURN r;
    ELSE RETURN nul_vector;
    END IF;
    END "and";

    FUNCTION "and" (l : IN bit_vector; r : IN bit)
    RETURN bit_vector IS
    BEGIN
    RETURN r and l;
    END "and";

    BEGIN
    obus <= ibus AND ibit;
    END demo3;

    ARCHITECTURE demo4 OF and_bus_with_bit IS
    FUNCTION "and" (l : IN bit; r : IN bit_vector)
    RETURN bit_vector IS
    BEGIN
    RETURN (r'RANGE => l) AND r;
    END "and";

    FUNCTION "and" (l : IN bit_vector; r : IN bit)
    RETURN bit_vector IS
    BEGIN
    RETURN r and l;
    END "and";

    BEGIN
    obus <= ibus AND ibit;
    END demo4;
     
    Egbert Molenkamp, Dec 22, 2003
    #3

  4. > I added 4 possible solutions (functions included in a test environment).


    Thanks a lot for your help so I have to program a litte bit to solve my
    problem. I have got another question perhaps you can give me a hint here

    As you can see I have got a Ripple Carry Adder Entity. Now with this entity
    for 1 bit I need instances with 2 bit, 3 bit 4 bit, 5 bit, 6 bit and 7 bit.
    I have added the code for the 2-bit Ripple Carry Adder which works fine. But
    is it somehow possible to do this with parameters? Because else I have to
    write an own architecture for each single RCA and I dont know if this is
    efficient

    Thanks again for your help

    library ieee;
    use ieee.std_logic_1164.all;

    entity RCA is port (
    x,y: in std_ulogic;
    cin: in std_ulogic;
    cout: out std_ulogic;
    sout: out std_ulogic
    );
    end RCA;

    architecture RTL of RCA is
    begin
    sout <= (x xnor y) xnor cin;
    cout <= (x nand y) nand ((x xnor y) or cin);
    end RTL;
    ------------------------------------------------------------------
    -- START: 2 Bit RCA
    ------------------------------------------------------------------
    library ieee;
    use ieee.std_logic_1164.all;

    entity BIT_2_RCA is port (
    x0,y0: in std_ulogic;
    x1,y1: in std_ulogic;
    cin: in std_ulogic;
    cout: out std_ulogic;
    s0,s1: out std_ulogic
    );
    end BIT_2_RCA;


    architecture RTL of BIT_2_RCA is

    component RCA
    port
    (
    x,y: in std_ulogic;
    cin: in std_ulogic;
    cout: out std_ulogic;
    sout: out std_ulogic
    );
    end component;

    signal carry : std_ulogic;
    signal carry1 : std_ulogic;

    begin
    RCA0: RCA port map (x=>x0,y=>y0,cin=>'0',cout=>carry,sout=>s0);
    RCA1: RCA port map (x=>x1,y=>y1,cin=>carry,cout=>carry1,sout=>s1);
    end RTL;
    ------------------------------------------------------------------
    -- ENDE: 2 Bit RCA
    ------------------------------------------------------------------
     
    Klaus Kleiner, Dec 22, 2003
    #4
  5. "Klaus Kleiner" <> schreef in bericht
    news:bs6ndn$a7li2$-berlin.de...
    >
    > > I added 4 possible solutions (functions included in a test environment).

    >
    > Thanks a lot for your help so I have to program a litte bit to solve my
    > problem. I have got another question perhaps you can give me a hint here
    >
    > As you can see I have got a Ripple Carry Adder Entity. Now with this

    entity
    > for 1 bit I need instances with 2 bit, 3 bit 4 bit, 5 bit, 6 bit and 7

    bit.
    > I have added the code for the 2-bit Ripple Carry Adder which works fine.

    But
    > is it somehow possible to do this with parameters? Because else I have to
    > write an own architecture for each single RCA and I dont know if this is
    > efficient
    >


    Use a generic in the entity:

    ENTITY ... IS
    GENERIC (w : integer := 8);
    PORT (x,y : std_logic_vector(w-1 DOWNTO 0); etc.

    In the architure you can use a GENERATE statement something like:

    ARCHITECTURE ...
    BEGIN
    label_required : FOR i IN 1 TO w GENERATE
    inst: RCA PORT MAP (x(i),...)
    END GENERATE;

    The first and last instantantiation is probable a little bit different.

    However, consider NOT using this approach (except for the generic in the
    entity)!

    There are packages available, i.e. numeric_std, that can handle your
    problem.
    If X and Y are vectors of type std_logic_vector you can write
    unsigned(X) + unsigned (Y)
    (of in case you use the synops package std_logic_unsigned, you can write: X
    + Y)
    The synthesis tool will recognise the adder.

    Egbert Molenkamp
     
    Egbert Molenkamp, Dec 22, 2003
    #5

  6. > There are packages available, i.e. numeric_std, that can handle your
    > problem.
    > If X and Y are vectors of type std_logic_vector you can write
    > unsigned(X) + unsigned (Y)
    > (of in case you use the synops package std_logic_unsigned, you can write:

    X
    > + Y)
    > The synthesis tool will recognise the adder.


    Thanks again for your tip, but i have to use a a Carry Select Adder which
    consists of 2 2-bit Ripple Carry Adder, 2 3-bit Ripple Carry Adder, 2 4-bit
    Ripple Carry Adder, 4 5-bit Ripple Carry Adder, 2 6-bit Ripple Carry Adder,
    2 7-bit Ripple Carry Adder. So i cant do this with a simple adder....
     
    Klaus Kleiner, Dec 22, 2003
    #6
  7. Klaus Kleiner wrote:

    > Thanks again for your tip, but i have to use a a Carry Select Adder which
    > consists of 2 2-bit Ripple Carry Adder, 2 3-bit Ripple Carry Adder, 2 4-bit
    > Ripple Carry Adder, 4 5-bit Ripple Carry Adder, 2 6-bit Ripple Carry Adder,
    > 2 7-bit Ripple Carry Adder. So i cant do this with a simple adder....


    What is the source of this curious constraint?

    -- Mike Treseler
     
    Mike Treseler, Dec 22, 2003
    #7
  8. Mike Treseler wrote:
    >
    > Klaus Kleiner wrote:
    >
    > > Thanks again for your tip, but i have to use a a Carry Select Adder which
    > > consists of 2 2-bit Ripple Carry Adder, 2 3-bit Ripple Carry Adder, 2 4-bit
    > > Ripple Carry Adder, 4 5-bit Ripple Carry Adder, 2 6-bit Ripple Carry Adder,
    > > 2 7-bit Ripple Carry Adder. So i cant do this with a simple adder....

    >
    > What is the source of this curious constraint?


    Curious constraints are often features of homework problems.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
     
    Tim Hubberstey, Dec 23, 2003
    #8
  9. Klaus Kleiner

    Steve Harrad Guest


    > > What is the source of this curious constraint?

    >
    > Curious constraints are often features of homework problems.


    No it isn't a homework. Its a project and we have to build an Multiplier in
    GF(2^m) for the LEON Processor. And therefore for summing up the final carry
    and sum array we need a Carry Select adder which consists of different
    Ripple Carry Adders
     
    Steve Harrad, Dec 23, 2003
    #9
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