Physical Compiler Vs Design Complier

Discussion in 'VHDL' started by whizkid, Nov 3, 2004.

  1. whizkid

    whizkid Guest

    Can anyone pointout the practical differences? I am now synthesising a
    design with TSMC 13u library with Design Compiler? What difference in
    results can I expect if I use physical Compiler.

    thanks
    whizkid
     
    whizkid, Nov 3, 2004
    #1
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  2. whizkid

    Tom Verbeure Guest

    If you provide a floorplan to Physical compiler, it will estimate the
    loading of nets according to actual placement of cells instead of
    statistical wireload models. This generally results in faster maximum
    speeds of the final design.

    Tom
     
    Tom Verbeure, Nov 3, 2004
    #2
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