Pin Locking on a FPGA

[bob_shuler]

A quick question for the group:

With the flexibility of today's FPGAs, is it still better to do the
VHDL or Verlog design through Synthesis and then lock pins on the FPGA
or could pins be locked on the FPGA before the design is synthesized?

I looking for the quickest way to get to a PCB. My design has various
buses. One of the buses is PCI.

Thanks,
Robert

 

[Mike Treseler]

With the flexibility of today's FPGAs, is it still better to do the
VHDL or Verlog design through Synthesis and then lock pins on the FPGA
or could pins be locked on the FPGA before the design is synthesized?

I go with the flow when I can, but most pin constraints can be
made to work if you need them.

I looking for the quickest way to get to a PCB. My design has various
buses. One of the buses is PCI.

If you have a preliminary place+route, use
that as a starting point, then fix
up the connectors etc. as needed.
I like to keep constraints out of the
source code.

-- Mike Treseler

 

[Andy]

I usually let the PCB set the pinout (within limits). However, I always
constrain the fpga P&R to the pcb pinout, and verify placement and
timing prior to releasing the PCB to fab. We have a bit-sliced, board
schematic symbol for the fpga that automatically constrains IO pin
swapping during PCB layout to like-powered IO banks. That helps a lot.

Andy

 

[Weng Tianxiang]

Hi Andy,
Could you please give more details on how it automatically constrains
IO pin swapping during PCB layout.

Both of me, FPGA designer and the engineer who is responsible for PCB
layout, spent a lot of time repeatedly checking the pin positions with
FPGA pin output files. When the number of pins reaches more that 800,
it is very time-comsuming.

I would like to learn from your experiences.

Weng

 

[Andy]

Unless you use Cadence ConceptHDL (now called Allegro Design Entry
HDL), my method may not make sense to you or your schematic tool.

Our FPGA schematic model has multiple symbol versions for different
parts of the FPGA. One for the config/jtag pins, one for an IO pin,
one for a Vcco (bank power) pin, and one for MGT IO. The first version
is only used once per FPGA on the board. You use as many of the other
three versions as are required to represent your connections (e.g. one
IO version for each IO pin you use, etc.) The IO symbol version has an
IO pin and a Vcco pin on it. The Vcco pin # is common to all IO pin #s
in the same bank. Cadence only allows pin swapping between functions
that have the same signal on their common pin(s) (i.e. their Vcco pins
are hooked up to the same power rail). The Vcco symbol version is used
to add all the extra Vcco pins per bank that your FPGA requires. It has
two pins also, one that is the same common vcco pin as the IO slice
uses, and the other is an "extra" Vcco pin to represent the other vcco
pins in that bank. The symbol has a property that ensures that the
extra and common Vcco pins are shorted together, to make sure that all
Vcco pins of a bank receive the same power.

Hope this made sense, but if you don't use Cadence, it might not...
Something similar can probably be done in Mentor schematics, but I
don't know how.

As for checking the pinout of the FPGA design vs the board netlist, it
is MUCH easier if your net names connected to the FPGA on the board
match the port names of the FPGA design. Then you can extract a
netlist of all connections to the FPGA, and compare it with the pin
report of the FPGA more easily. I have no idea of the capabilities of
the lower-tier schematic capture tools.

Andy

 

[Weng Tianxiang]

Hi Andy,
Thank you for your advice.

I don't know what tools our PCB engineers are using. At least for the
latest project with more than 800 pins there is no error. But I really
spent a lot of time checking the pin list with my FPGA pin list several
times. That was the task the hardware design engineer gave me to do. I
think they use the same right method as yours.

Weng