pipe line in VHDL

Discussion in 'VHDL' started by minombre, Oct 3, 2008.

  1. minombre

    minombre

    Joined:
    Oct 2, 2008
    Messages:
    2
    Im making the description of a multiplier and I need to make it more efficient using a pipeline. how can i make code of a pipeline Im very confused about it (its for a homework). could someone submit some code of an entity that uses a pie line???:saint:
     
    minombre, Oct 3, 2008
    #1
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