pipeline and low power relationship

Discussion in 'VHDL' started by fl, Feb 18, 2014.

  1. fl

    fl Guest

    Hi,

    Excuse me I post this question here because I think it is related to VHDL design than other algorithm groups. Pipeline is heavily used in VHDL design.I read the book "VLSI digital signal processing systems" by K. K. Parhi. It says that pipeline and parallel design can lower power consumption. More specifically, pipeline can "increase the sample clock or to reduce the power consumption at same speed." (Parhi)

    I personally have a guess about the above statement. Is it implicitly assuming that power consumption increases very fast with sample clock? Anyway, Istill cannot imagine "to reduce the power consumption at same speed."

    I do not find relevant example on that book or on-line. Could you explain it to me?




    Thanks,
    fl, Feb 18, 2014
    #1
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  2. fl

    Guest

    Am Dienstag, 18. Februar 2014 20:56:39 UTC+1 schrieb fl:
    > Hi,
    >
    >
    >
    > Excuse me I post this question here because I think it is related to VHDLdesign than other algorithm groups. Pipeline is heavily used in VHDL design. I read the book "VLSI digital signal processing systems" by K. K. Parhi.It says that pipeline and parallel design can lower power consumption. More specifically, pipeline can "increase the sample clock or to reduce the power consumption at same speed." (Parhi)
    >
    >
    >
    > I personally have a guess about the above statement. Is it implicitly assuming that power consumption increases very fast with sample clock? Anyway,I still cannot imagine "to reduce the power consumption at same speed."
    >
    >
    >
    > I do not find relevant example on that book or on-line. Could you explainit to me?
    >
    >
    >
    >
    >
    >
    >
    >
    >
    > Thanks,


    Hi,
    higher clock rates cause higher power consumption in a CMOS device.
    That's a trivial fact.
    If it increases "very fast" depends on your interpretation of that phrase.

    Pipelined designs can be used in two ways.
    1) To increase the sampling or data rate.
    Here you spend additional hardware for each computational step, where each step uses one clock cycle.
    Therefore the data rate is equal to the clock rate, which can become very high.
    High data rate plus increased design size cause high power consumption.

    2) However, if you decide to keep the data rate constant (low) the power losses due to CMOS transistor switching will stay low too. (Still there's some loss du to the higher number of registers.)
    The other option would be to save design space for the cost of a higher system clock rate depending on the number of required computational steps.
    sys_clk = datarate*N_steps

    Wether the second option works for you in order to save power depends on the technology you are using.
    You have some function of power/f per switching element.

    Now it depends on that function and your design wether spending additional HW at low frequencies saves energy compared to a small design running at a higher frequency.

    There might be some trade-off point for each technology and application, that needs to be calculated to make a reasonable decision.

    Have a nice synthesis
    Eilert
    , Feb 19, 2014
    #2
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