Pipelined signed multipliers

Discussion in 'VHDL' started by khodorf, Mar 3, 2009.

  1. khodorf

    khodorf

    Joined:
    Mar 3, 2009
    Messages:
    1
    Hello,

    I am trying to design a signed multiplier and I want to make it pipelined so I can improve its performance. I am experimenting with a Baugh-wooley multiplier but I am not quite sure how to go about this.

    How is it possible to specify the number of pipelining stages in the multiplier or do I have to add registers at every input and output?

    Any suggestions for this or other signed high performance multipliers is appreciated.

    Thanks
    Kaf
     
    khodorf, Mar 3, 2009
    #1
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