Pipelining in VHDL

Discussion in 'VHDL' started by koko, Apr 29, 2004.

  1. koko

    koko Guest

    can anyone suggest a good reference on pipelining (particulalr in VHDL)?

    - Kingsley
     
    koko, Apr 29, 2004
    #1
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  2. koko

    Jim Lewis Guest

    > can anyone suggest a good reference on pipelining (particulalr in VHDL)?
    Have you tried google?

    For some ideas about multipliers see:
    http://www.synthworks.com/papers

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Apr 29, 2004
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  3. koko

    mizocom Guest

    if you mean functional unit pipelining (i.e pipelined multiplier, divider)
    here is a simple example for pipelined multiplier
    at the rtl level one of the ways to implement pipelining
    is to add two (or more) registers at the end of the functional unit
    and let the synthesis software do something called register balancing
    by distributing the registers equally along the combinational logic path.
    for more info search for pipelined multiplier, register balancing.
    but in datapath pipelining you add and connect the registers yourself.

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;
    USE ieee.std_logic_unsigned.all;

    ENTITY pipe_mult IS

    port(a,b:in std_logic_vector(3 downto 0);
    clk:in std_logic;
    c:eek:ut std_logic_vector(7 downto 0));

    END pipe_mult ;


    ARCHITECTURE multiply OF pipe_mult IS

    signal d:std_logic_vector(7 downto 0);

    BEGIN

    process(a,b,clk)
    begin
    --this is called register inference

    if clk'event and clk='1' then
    d<=a*b;
    c<=d;
    end if;

    end process;

    END multiply;
    mizocom

    "koko" <> wrote in message news:<c6prbi$8i7$>...
    > can anyone suggest a good reference on pipelining (particulalr in VHDL)?
    >
    > - Kingsley
     
    mizocom, Apr 29, 2004
    #3
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