pipelining

Discussion in 'VHDL' started by tulip, Nov 5, 2004.

  1. tulip

    tulip Guest

    hi,

    Can anyone please give the VHDL code for the following pipelined
    architecture:

    Input-->portmap"mmm"-->register1-->portmap"mmm"->register2

    --> portmap"mmm" -> output
    tulip, Nov 5, 2004
    #1
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