Please help: Error during synthesizing program with sensitivity list in process

Discussion in 'VHDL' started by Lakshmanan.ag, Apr 11, 2010.

  1. Lakshmanan.ag

    Lakshmanan.ag

    Joined:
    Apr 11, 2010
    Messages:
    1
    Hello everyone,

    I am a student and I am trying to build a model of olfactory lobe of brain for my project using FPGA. Firstly, I have to build a model of singular neuron and later connect these blocks in order to build the lobe. In order to build a neuron model I am asked to model the synapse(junction of connection between two neurons), soma(neuron body), axon(long tail of neuron) seperatley and later join them to obtain the neuron model. I wrote the following code (below)for modelling synapse. When I simulate it by suitable test bench, I get the expected beautiful sawtooth waveform using ModelSim.

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity synapse_model_vhdl is

    port( syn_current : out std_logic_vector(31 downto 0);
    syn_in : in std_logic;
    syn_weight : in std_logic_vector(31 downto 0)
    );

    end synapse_model_vhdl;


    architecture Behavioral of synapse_model_vhdl is

    signal adsub_in : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
    signal adsub_out : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
    signal acc_prev_out : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
    signal acc_curr_out : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
    signal shift_out : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
    constant tau : integer := 11;
    signal syn_clk : std_logic;
    signal shift_process: bit_vector(31 downto 0);
    signal shift_temp : bit_vector(31 downto 0);
    begin
    syn_clk <= syn_in;
    synapse_calc: process is
    begin
    if syn_clk = '0' then
    adsub_in <= "00000000000000000000000000000000";
    elsif syn_clk = '1' then
    adsub_in <= syn_weight;
    end if;
    shift_process <= to_bitvector(acc_prev_out); -- \\
    shift_temp <= shift_process sra tau; -- Shifter code
    shift_out <= to_stdlogicvector(shift_temp); -- //
    adsub_out <= adsub_in - shift_out; -- Subtractor block
    acc_curr_out <= acc_prev_out + adsub_out; -- Accumulator block
    wait for 500 ps; -- For simulation only
    acc_prev_out <= acc_curr_out;
    wait for 500 ps; -- For simulation only
    end process synapse_calc;
    syn_current <= acc_curr_out;

    end Behavioral;


    The problem is:

    I am experiencing difficulty while trying to synthesize-XST (viewing the RTL schematic, technology schematic of) the synapse model.

    Xilinx ISE shows compilation error while I have 'wait for 500 ps' during RTL schematic generation stages:

    ERROR:HDLParsers:1015 - "D:/Xilinx92i/synapse_model_final/synapse_model_vhdl_code.vhd" Line 69. Wait for statement unsupported.
    ERROR:HDLParsers:1015 - "D:/Xilinx92i/synapse_model_final/synapse_model_vhdl_code.vhd" Line 71. Wait for statement unsupported.


    Hence, I replaced the 'wait for 500 ps' statement by the sensitivity list parameters as shown below:


    synapse_calc: process(syn_in,syn_clock,acc_prev_out,adsub_in,shift_temp,shift_out,adsub_out,shift_process)

    begin
    if syn_in = '0' then
    adsub_in <= "00000000000000000000000000000000";
    elsif syn_in = '1' then

    adsub_in <= syn_weight;
    end if;

    if syn_clock = '1' then
    shift_process <= to_bitvector(acc_prev_out); -- \\
    shift_temp <= shift_process srl tau; -- Shifter code
    shift_out <= to_stdlogicvector(shift_temp); -- //

    adsub_out <= adsub_in - shift_out; -- Subtractor block

    acc_curr_out <= acc_prev_out + adsub_out; -- Accumulator block
    --wait for 500 ps; -- For simulation only
    acc_prev_out <= acc_curr_out after 800 ps;
    --wait for 500 ps; -- For simulation only
    end if;
    end process synapse_calc;


    Now, the problem is:

    I am not getting the same simulation waveforms in ModelSim.

    I am concerned that I would get totally bizzarre results while I implement synapse on the board which could be totally different from simulation. I am new to FPGA and this is my first project. Please somebody help me solve this problem with synapse so that I can proceed for other components and build the neuron.

    Thanks,
    A.G.Lakshmanan
     
    Lakshmanan.ag, Apr 11, 2010
    #1
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  2. Lakshmanan.ag

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    Synthesis Error

    "Wait for" is not synthesizable. Remember you are synthesizing hardware. The synthesis tool does not "know" how you want to synthesize the delay. The typical way to implement a synthesizable delay is to use a counter that counts clocks. The counter can be a down counter loaded with the desired delay in clock periods. Start the counter when the delay should begin and when the count reaches zero the delay is completed.
     
    eliascm, Apr 12, 2010
    #2
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