Please Help in understanding a VHDL syntax

Discussion in 'VHDL' started by buddy249, Jun 22, 2009.

  1. buddy249

    buddy249

    Joined:
    Jun 22, 2009
    Messages:
    1
    i'm new to Vhdl programming... i need to understand a vhdl program for completion of my miniproject..
    so please help me......

    entity aFifo is
    generic (
    DATA_WIDTH :integer := 8;
    ADDR_WIDTH :integer := 4
    );


    what does generic mean? and where can we use that syntax?

    type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);

    and please explain the above statement......
    buddy249, Jun 22, 2009
    #1
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  2. buddy249

    debayan_p

    Joined:
    Jun 2, 2009
    Messages:
    23
    ha ha ha ha......U have copied the code from asic-world.com -- Memory design section !!

    Instead of doing such things 1st clear ur fundamentals. Take any good VHDL book and go through it. Study for a week. U'll undersatand most of the things !

    I am telling this for ur own good.....it'll help u in future !

    All t best
    debayan_p, Jun 23, 2009
    #2
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