Please help me in registerfile vhdl program

Discussion in 'VHDL' started by madboy, Oct 2, 2006.

  1. madboy

    madboy

    Joined:
    Oct 2, 2006
    Messages:
    1
    Hi everybody,
    I am quite new to VHDL and I have some questions. I am trying to

    Develop VHDL code (behavioural mode only) for a Register File with 256 locations, each location can hold 8 Bytes. Initialize all the locations with "0" and test for writing(reading) to(from) it at least 5 times.

    Write/read time equals 1 clk cycle

    If it is not possible to give full length solution, Atleast post brief idea
     
    Last edited: Oct 2, 2006
    madboy, Oct 2, 2006
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. casioculture@gmail.com
    Replies:
    4
    Views:
    565
    Chris Uppal
    May 5, 2005
  2. KK
    Replies:
    2
    Views:
    706
    Big Brian
    Oct 14, 2003
  3. MuZZy
    Replies:
    7
    Views:
    1,822
    Mike Hewson
    Jan 7, 2005
  4. afd
    Replies:
    1
    Views:
    8,547
    Colin Paul Gloster
    Mar 23, 2007
  5. imaginary
    Replies:
    0
    Views:
    862
    imaginary
    Dec 2, 2009
Loading...

Share This Page