Hi everybody,
I am quite new to VHDL and I have some questions. I am trying to
Develop VHDL code (behavioural mode only) for a Register File with 256 locations, each location can hold 8 Bytes. Initialize all the locations with "0" and test for writing(reading) to(from) it at least 5 times.
Write/read time equals 1 clk cycle
If it is not possible to give full length solution, Atleast post brief idea
I am quite new to VHDL and I have some questions. I am trying to
Develop VHDL code (behavioural mode only) for a Register File with 256 locations, each location can hold 8 Bytes. Initialize all the locations with "0" and test for writing(reading) to(from) it at least 5 times.
Write/read time equals 1 clk cycle
If it is not possible to give full length solution, Atleast post brief idea
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