please help me out

[Lovely Robot]

hey friends , I'm trying to design an interface between a ps2 keyboard
and the digilent DIO5 board which contains a Xilinx CoolRunner CPLD.

but the Xilinx synthesis tool Xst drove me crazy
here are the errors I got followed by my VHDL code
please help me


WARNING:Xst:1710 - FF/Latch (without init value) has a constant value
of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming,
FF/Latch (without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without
init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due

to other FF/Latch trimming, FF/Latch (without init value) has a
constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch

trimming, FF/Latch (without init value) has a constant value of 0 in
block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch
(without init value) has a constant value of 0 in block .
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without
init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due

to other FF/Latch trimming, FF/Latch (without init value) has a
constant value of 0 in block . WARNING:Xst:1291 - FF/Latch is
unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in
block . WARNING:Xst:1291 - FF/Latch is unconnected in block .
WARNING:Xst:1291 - FF/Latch is unconnected in block . Optimizing unit
....
=========================================================================

* Final Report *


here is my code
----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;


entity kbd is port(
kclk,kd,uclk : in std_logic; -- keyboard clk , keyboard data ,
universal clk ,respectively
s_ca: out std_logic_vector(7 downto 0); -- seven-segments
display
s_an: out std_logic_vector(3 downto 0)-- seven-segments anode
);
end kbd;


--}} End of automatically maintained section


architecture kbd_archi of kbd is


signal ready : std_logic := '1'; -- 11 bits have been received
signal data : std_logic_vector(7 downto 0); -- ASCCI character
pressed
constant keyup : std_logic_vector := x"f0"; -- keyup character
signal dr : std_logic_vector(10 downto 0); -- a temporary register to
hold the data coming from the kbd
signal count : std_logic_vector(1 downto 0) := "00"; -- to indicate
that the key up has been received and expecting the final data
signal ssg : std_logic_vector(7 downto 0); -- seven-segments temp.

register
begin


p1 : process(kclk)
subtype int is integer range 0 to 11;
variable cnt : int := 0;
begin
if falling_edge(kclk) then
if cnt /= 11 then
dr(cnt) <= kd;
cnt := cnt + 1;
ready <= '0';
else
ready <= '1';
cnt := 0;
end if;
end if;


end process p1;


p2: process(ready)
begin
if ready ='1' then
if dr(8 downto 1) = keyup then
count <= count + 1;
ready <='0';
else
if count = "01" Then count <= count + 1;
ready <= '0';
end if;
end if;
else
dr <= dr;
end if;
end process p2;


p3: process(uclk)
begin
if rising_edge(uclk) then
if count = "10" then
data <= dr( 8 downto 1);
count <="00";
else
data <= data;
end if;
end if;
end process p3;


s_an <="1110";


with data select
ssg <= "00111111" when x"45" ,
"00000110" when x"16" ,
"01011011" when x"1E" ,
"01001111" when x"26" ,
"01100110" when x"25" ,
"01101101" when x"2E" ,
"01111101" when x"36" ,
"00000111" when x"3D" ,
"00000111" when x"3E" ,
"00000111" when x"46" ,
"00000000" when others;


s_ca <= not ssg;


end kbd_archi;

 

[vipinlal]

here is your solution..
vhdlguru.blogspot.com/2010/03/synthesis-warning-fflatch-has-constant.html