Yes Andy, this is what I meant.
mmm, Ok so I declared this range in my entity,
Input1 : in STD_LOGIC_VECTOR (7 downto 0);
Then I do something like this:
add(Input1, Result);
and procedure "add" is
procedure add (v : in std_logic_vector; res: out integer) is
alias v1 : std_logic_vector (7 downto 0) is v;
Am I correct if I assume that I should get the vector "Input1" in "v1"
after calling the procedure "add"?
Xiao
By "want no range" do you mean you want undeclared range? If so, that
works fine, but not for the top level entity. If you have
unconstrained ports, their range is defined in the instantiation. A
top level entity is not instantiated anywhere, so there is no
definition for the range.
Andy
Yes, you are correct. I assume your example procedure is just an
academic exercise? Otherwise, the code will not elaborate if Input1 is
anything but 8 bits long. You can get the range (or length, etc.) of
an unconstrained port by using the appropriate attribute of it. In
this case, v'length would be 8 inside this instantiation of add(). A
better alias declaration would be:
alias v1: std_logic_vector(v'length - 1 downto 0) is v;
Which would normalize the range of v1 to be the correct length, but
with downto direction, and ending at 0, no matter what the index range
of input1 was (i.e. input1 might have been slv(8 to 15). This is
always a good thing to do inside architectures or subprograms with
unconstrained ports, if your implementation relies on a specific index
ordering, etc. Most folks do it with a variable declaration,
initialized to the value of the port, but either way works, so long as
your tool supports it.
variable v1 : std_logic_vector(v'length - 1 downto 0) := v;
Andy