PLL and another design together

Discussion in 'VHDL' started by John K, Nov 13, 2006.

  1. John K

    John K Guest

    I've designed a PLL and want to give the clock output from there to an
    another design. What is the proper way to design that ???
    Defining signal and give tat to the other design.. will it work ??? Or,
    should I define another entity and map the ports.. Pliz show me the
    way ...
    John K, Nov 13, 2006
    #1
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  2. John K

    Andy Guest

    In most cases, you would encapsulate your PLL in an
    entity/architecture, and instantiate that entity in the target design.
    The only other general choice is a concurrent procedure call (with the
    procedure defined in a package referenced by the target design), which
    is limited in functionality, especially wrt synthesis.

    Andy


    John K wrote:
    > I've designed a PLL and want to give the clock output from there to an
    > another design. What is the proper way to design that ???
    > Defining signal and give tat to the other design.. will it work ??? Or,
    > should I define another entity and map the ports.. Pliz show me the
    > way ...
    Andy, Nov 13, 2006
    #2
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