PLL in CPLD

Discussion in 'VHDL' started by Kriki, Sep 16, 2004.

  1. Kriki

    Kriki Guest

    I need to program a digital PLL in a CPLD.

    I tryed to use an external Clock Generator @ 24.576 MHZ, but the data
    signal is not exactly that frequency.

    So can anyone help me with that problem ???
    Kriki, Sep 16, 2004
    #1
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