plz clarify this doubt in vhdl

[chaitanyakurmala]

dear all
behavior: process(clk_in)

variable fifo_index : natural := 0;
--variable i : natural ;
variable fifo_buffer : buffer_type;
--variable req_temp : std_logic := '0';

in above fifo_index is defined as variable .so will fifo_index will be
initiated as zero. so in program fifo_index has been changed to some
other value say 10.
my doubt is that again when process is triggered for the second time
will fifo_index be 10 or it is again initialized to 0.
thank you

 

[Jonathan Bromley]

dear all
behavior: process(clk_in)

variable fifo_index : natural := 0;
--variable i : natural ;
variable fifo_buffer : buffer_type;
--variable req_temp : std_logic := '0';

in above fifo_index is defined as variable .so will fifo_index will be
initiated as zero. so in program fifo_index has been changed to some
other value say 10.
my doubt is that again when process is triggered for the second time
will fifo_index be 10 or it is again initialized to 0.

No doubt. All variables are initialised to their leftmost value,
unless you specify otherwise. So fifo_index is unquestionably
initialised to 0 at time zero. It then retains its value across
executions of the process; it is NOT re-initialised when the
process re-starts.

Note, though, that initialisation of variables is NOT reliable in
synthesis. It is 100% ok for simulation, but synthesis usually
ignores initialisation that's part of a declaration. You need to
perform an explicit initialisation action as the result of a reset.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.