plz hel me to design edgedetector

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Mar 16, 2007
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sir,

i need to design a edgedetector which has 2 inputs clock and trigger. when trigger becomes high the output should go high and it remains there for 10sec. after that it should go low. it is not a retriggerable edgedetector.

i'm sending a program that i got from one site. but there is a problem when i down loding it in cpld. the problem is that it get triggered whenever it goes high and also when it goes zero. that means when ever there is an event in input the out put goes high. my requirment is it should go high only when there is an event in trigger and trigger='1'.

plz help me. 'm new to vhdl thats why........


entity edgedet is
port( ip,clk: in std_logic;
op: out std_logic);
end edgedet;
architecture Behavioral of edgedet is
signal s,r:std_logic;
begin
--for making output high
process(ip, r)
begin
if r = '1' then --if r ==1 then
output==0
s <= '0';
elsif ip'event and ip = '1' then
s <= '1';
end if;
end process;

process(ip, clk, s)
begin
if clk'event and clk = '1' then
if r= '1' then
r <= '0';
else
r <= s;
end if;
end if;
end process;

op<= s;

end Behavioral;



thank you
sreejisha
 

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