pn sequence

Discussion in 'VHDL' started by J.Ram, Sep 12, 2006.

  1. J.Ram

    J.Ram Guest

    Hi all,
    my objective is to get outpn value when rising_edge of clk and low
    reset.
    when i written code , and in simulation result outpn value is comes
    after one clk
    cycle after reset goes to low, but my need is to get outpn at the
    moment reset goes low.
    here is my code.
    entity pn is
    port(
    clk,reset : in std_logic;
    outpn : std_logic);
    end pn;
    architecture test of pn is
    type data is array(1 to 6) of std_logic;
    signal buff : data;
    begin
    process(clk,reset)
    variable input : std_logic;
    begin
    if reset = '1' then
    outpn <= 'X';
    elsif clk'event and clk ='1' then
    input := buff(1) xor buff(6);
    buff(1) <= input;
    buff(2) <= buff(1);
    buff(3) <= buff(2);
    buff(4) <= buff(3);
    buff(5) <= buff(4);
    buff(6) <= buff(5);
    end if;
    outpn <= buff(6);]
    end process;
    end test;
     
    J.Ram, Sep 12, 2006
    #1
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  2. J.Ram

    uvbaz Guest

    J.Ram schrieb:

    > Hi all,
    > my objective is to get outpn value when rising_edge of clk and low
    > reset.
    > when i written code , and in simulation result outpn value is comes
    > after one clk
    > cycle after reset goes to low, but my need is to get outpn at the
    > moment reset goes low.
    > here is my code.
    > entity pn is
    > port(
    > clk,reset : in std_logic;
    > outpn : std_logic);
    > end pn;
    > architecture test of pn is
    > type data is array(1 to 6) of std_logic;
    > signal buff : data;
    > begin
    > process(clk,reset)
    > variable input : std_logic;
    > begin
    > if reset = '1' then
    > outpn <= 'X';
    > elsif clk'event and clk ='1' then
    > input := buff(1) xor buff(6);
    > buff(1) <= input;
    > buff(2) <= buff(1);
    > buff(3) <= buff(2);
    > buff(4) <= buff(3);
    > buff(5) <= buff(4);
    > buff(6) <= buff(5);
    > end if;
    > outpn <= buff(6);]
    > end process;
    > end test;


    is this what do you want:

    library ieee;
    use ieee.std_logic_1164.all;

    entity pn is
    port
    (
    clk: in std_logic;
    reset: in std_logic;
    outpn: out std_logic
    );
    end pn;

    architecture test of pn is
    type data is array(1 to 6) of std_logic;
    signal buff : data;
    begin
    process(clk, reset)
    variable input : std_logic;
    begin
    if reset = '1' then
    outpn <= '0';
    elsif( (clk'event and clk ='1') or (reset'event and reset = '0') )
    then
    input := buff(1) xor buff(6);
    buff(1) <= input;
    buff(2) <= buff(1);
    buff(3) <= buff(2);
    buff(4) <= buff(3);
    buff(5) <= buff(4);
    buff(6) <= buff(5);
    outpn <= buff(6);
    end if;
    end process;
    end test;
     
    uvbaz, Sep 12, 2006
    #2
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  3. uvbaz schrieb:
    > elsif( (clk'event and clk ='1') or (reset'event and reset = '0') )


    You need a very good synthesis tool to synthesis the code in the
    desired way. (and a technology allowing logic in the clock path). You
    will further have big trouble with timig analysis of this construct.

    I guess[1] the real code should be

    signal PNcount : std_ulogic_vector(5 downto 0);
    process (clk, Rst)
    if reset_active then
    PNcount<= Seed;
    elsif rising_edge(Clk) then
    PNcount <= PNcount(4 downto 0) & (PNcount(5) XOR PNCount(0);
    end if;
    end process
    Outpn<=PNcount(5);

    bye Thomas

    [1] The OP was a bit confuse for me about what he really wanted
     
    Thomas Stanka, Sep 12, 2006
    #3
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