X
XYZ
Hello,
I'm trying to simulate asynchronous dual-rail latch that I wrote. I
created following test bench (only part of test bench architecture):
architecture behavior of test_latch is
component latch is
port (
ack_o: in std_logic;
ack_i: out std_logic;
input : in dual_rail_vector(2 downto 0);
output : out dual_rail_vector(2 downto 0)
);
end component;
signal uut_input, uut_output : dual_rail_vector(2 downto 0);
signal uut_ack_o, uut_ack_i : std_logic;
begin
UUT : latch
port map (
ack_o => uut_ack_o,
ack_i => uut_ack_i,
input => uut_input,
output => uut_output
);
and I get "Port 'input' is not constrained" ModelSim error. In fact,
latch entity has input and output ports unconstrained, i.e.
entity latch is
port (
ack_o: in std_logic;
ack_i: out std_logic;
input : in dual_rail_vector;
output : out dual_rail_vector
);
end;
When I make an assignment input => uut_input in my test bench (input
unconstrained, uut_input constrained (2 downto 0) ) doesn't it make the
input itself constrained? I thought it does.
How to solve it? Is it necessary to use generic width for all components
and get rid of unconstrained inputs/outputs?
Thanks
I'm trying to simulate asynchronous dual-rail latch that I wrote. I
created following test bench (only part of test bench architecture):
architecture behavior of test_latch is
component latch is
port (
ack_o: in std_logic;
ack_i: out std_logic;
input : in dual_rail_vector(2 downto 0);
output : out dual_rail_vector(2 downto 0)
);
end component;
signal uut_input, uut_output : dual_rail_vector(2 downto 0);
signal uut_ack_o, uut_ack_i : std_logic;
begin
UUT : latch
port map (
ack_o => uut_ack_o,
ack_i => uut_ack_i,
input => uut_input,
output => uut_output
);
and I get "Port 'input' is not constrained" ModelSim error. In fact,
latch entity has input and output ports unconstrained, i.e.
entity latch is
port (
ack_o: in std_logic;
ack_i: out std_logic;
input : in dual_rail_vector;
output : out dual_rail_vector
);
end;
When I make an assignment input => uut_input in my test bench (input
unconstrained, uut_input constrained (2 downto 0) ) doesn't it make the
input itself constrained? I thought it does.
How to solve it? Is it necessary to use generic width for all components
and get rid of unconstrained inputs/outputs?
Thanks