Port map with combining

Discussion in 'VHDL' started by Sylvain Munaut, Aug 5, 2004.

  1. Hi,

    I have a component that wants a std_logic_vector of 4 bits.
    Now, I have a std_logic and a std_logic_vector of 3 bits.

    Is it possible to port map it without defining an intermediate signal, like

    signal vect : std_logic_vector(2 downto 0);
    signal bit : std_logic;

    .... port map (
    vect4bit => bit & vect,
    ...
    );

    But that doesn't work ...



    Sylvain Munaut
    Sylvain Munaut, Aug 5, 2004
    #1
    1. Advertising

  2. Sylvain Munaut

    Jim Lewis Guest

    Sylvain,
    Assuming that vect4bit has the range 3 downto 0:

    port map (
    vect4bit(3) => bit,
    vect4bit(2 downto 0) => vect,
    . . .
    ) ;

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

    > Hi,
    >
    > I have a component that wants a std_logic_vector of 4 bits.
    > Now, I have a std_logic and a std_logic_vector of 3 bits.
    >
    > Is it possible to port map it without defining an intermediate signal, like
    >
    > signal vect : std_logic_vector(2 downto 0);
    > signal bit : std_logic;
    >
    > ... port map (
    > vect4bit => bit & vect,
    > ...
    > );
    >
    > But that doesn't work ...
    >
    >
    >
    > Sylvain Munaut
    Jim Lewis, Aug 5, 2004
    #2
    1. Advertising

  3. Jim Lewis wrote:
    > Sylvain,
    > Assuming that vect4bit has the range 3 downto 0:
    >
    > port map (
    > vect4bit(3) => bit,
    > vect4bit(2 downto 0) => vect,
    > . . .
    > ) ;
    >
    > Cheers,
    > Jim


    Exactly thanks !

    I havent't seen such an example in tutorials/intro, pity ;(


    Sylvain
    Sylvain Munaut, Aug 6, 2004
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. John T. Goodman

    Overhead of 4-port over 2-port SRAM

    John T. Goodman, Jan 25, 2005, in forum: VHDL
    Replies:
    0
    Views:
    596
    John T. Goodman
    Jan 25, 2005
  2. Sean Wolfe
    Replies:
    1
    Views:
    2,249
    Joerg Jooss
    Apr 28, 2005
  3. b3ny
    Replies:
    11
    Views:
    920
    Babu Kalakrishnan
    Nov 20, 2004
  4. Gerald Klix
    Replies:
    0
    Views:
    1,269
    Gerald Klix
    Oct 26, 2005
  5. Pom
    Replies:
    2
    Views:
    1,654
    Bas-i
    Jan 31, 2007
Loading...

Share This Page