Port map with if and process

Discussion in 'VHDL' started by Vindog67, Oct 12, 2011.

  1. Vindog67

    Vindog67

    Joined:
    Oct 12, 2011
    Messages:
    1
    Hi , I am currently working on FIR filter on vhdl on FPGA,(and yes i suck on programming)
    Just wondering is it possible to do the if loop with port map?

    here is my code. it keep telling me there is syntax error over there

    Line 134: Syntax error near "PORT".
    Line 139: Syntax error near ";".

    Allocate_process : process(clka)
    begin
    Multi_Coeff1(index)<= Temp;
    if (index>= 23 ) then
    SigState(0)<= '1';
    end if;
    end process Allocate_process;


    Multi1_process : process
    begin
    if(sigSTATE(0)='1')then

    here>Alloc1:InputX_ROM PORT MAP
    (
    clka => clka,
    addra => counter,
    douta => Input
    and here> );
    end if;
    end process Multi1_process;


    PLEASE HELP ME
     
    Vindog67, Oct 12, 2011
    #1
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