Port Mapping

[kwaj]

Hi ya,

I am newbie, still trying to get my head around the language. I am trying to
figure out how to connect two components together, mainly for a testbench
configuration. I have a design titled 'dds' in a folder labelled 'work'. The
entity of dds is;

entity dds is
port (
Clk,Clr: in std_logic;
Load: in std_ulogic;
Data_in: in std_ulogic_vector(15 downto 0);
Data_out: out std_ulogic_vector(15 downto 0)
);
end dds;

The output vector is titled Data_out. How do I access the output of the
component, given its location in \work\?

cheers

 

[fabbl]

Follow this and it will answer your question:

entity whatever_bench is
end whatever_bench;

architecture whatever_bench of whatever_bench is

component dds --This is your component
port (
Clk,Clr: in std_logic;
Load: in std_ulogic;
Data_in: in std_ulogic_vector(15 downto 0);
Data_out: out std_ulogic_vector(15 downto 0)
);
end component;

signal dds_Clk, dds_Clr:std_logic
signal dds_Load: in std_ulogic;
signal dds_Data_in: in std_ulogic_vector(15 downto 0);
signal dds_Data_out: out std_ulogic_vector(15 downto 0)

signal dds_Clk2, dds_Clr2:std_logic
signal dds_Load2: in std_ulogic;
signal dds_Data_in2: in std_ulogic_vector(15 downto 0);
signal dds_Data_out2: out std_ulogic_vector(15 downto 0)

begin

U1: dds --Instantiate one
port map (Clk=>dds_Clk, Clr=>dds_Clr, Load=>dds_Load, Data_in=>dds_Data_in,
Data_out=>dds_Data_out);

U2: dds -- then another
port map (Clk=>dds_Clk2, Clr=>dds_Clr2, Load=>dds_Load2,
Data_in=>dds_Data_in2,
Data_out=>dds_Data_out2);

-- Now just connect them together like this...
dds_Data_in2<=dds_Data_out;

--etc....

end whatever_bench;


See?