Portable Coding Guidelines?

Discussion in 'VHDL' started by Roger, Dec 17, 2004.

  1. Roger

    Roger Guest

    I've been looking at coding guidelines for a large, very long-term
    project that will span multiple FPGA design ports. I've looked at the
    Reuse Methodology Manual and OpenMORE, and IEEE 1076.6, but I've
    recently come across this quote:

    http://www.us.design-reuse.com/news/news4537.html
    'Bricaud said he believes the third edition of the RMM will be the
    last. "This is the way you design down to 130 nanometers with IP
    reuse," he said. "But now we're going to 90 nm, and there are going to
    be dramatic changes in the design methodology. Physical effects are
    going to have to be taken into account early in the design cycle, and
    we don't have all the solutions." '

    FPGAs are at 90 nm now, and have been for sometime. So is RMM obsolete
    as a coding guideline? Was Bricaud only referring to the recent trend
    towards physical synthesis?

    If anyone out there has any real knowledge of VSIA's QIP, I would love
    to know how much it departs from RMM and OpenMORE as an actual coding
    guideline and what the timeline is for public use.

    I figure I'll be calling the vendors on this one, but how far off is
    vendor-compliance with IEEE 1076.6-2004?

    Thanks in advance.
     
    Roger, Dec 17, 2004
    #1
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