Possible Quartus Bug

Discussion in 'VHDL' started by Rob Gaddi, Aug 23, 2013.

  1. Rob Gaddi

    Rob Gaddi Guest

    Just wanted to make sure this is an actual bug before I report it to
    Altera.

    I'm compiling as VHDL-2008, and I'm getting the error message:
    type of identifier "A_i" does not agree with its usage as
    "std_logic_vector"

    What I've got is (in various and correct places):
    port A: inout std_logic_vector(31 downto 1);
    signal A_i: std_ulogic_vector(31 downto 1);
    A <= A_i when drive_addr else (others => 'Z');

    The error goes away when I forcibly cast A_i to std_logic_vector, but
    aren't they supposed to be compatible without a cast? Interestingly,
    I'm doing the same thing with some std_(u)logic signals, and they're
    working fine.

    Thanks,
    Rob

    --
    Rob Gaddi, Highland Technology -- www.highlandtechnology.com
    Email address domain is currently out of order. See above to fix.
    Rob Gaddi, Aug 23, 2013
    #1
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  2. Rob Gaddi

    HT-Lab Guest

    On 23/08/2013 00:57, Rob Gaddi wrote:
    > Just wanted to make sure this is an actual bug before I report it to
    > Altera.
    >
    > I'm compiling as VHDL-2008, and I'm getting the error message:
    > type of identifier "A_i" does not agree with its usage as
    > "std_logic_vector"
    >
    > What I've got is (in various and correct places):
    > port A: inout std_logic_vector(31 downto 1);
    > signal A_i: std_ulogic_vector(31 downto 1);
    > A <= A_i when drive_addr else (others => 'Z');
    >
    > The error goes away when I forcibly cast A_i to std_logic_vector, but
    > aren't they supposed to be compatible without a cast? Interestingly,
    > I'm doing the same thing with some std_(u)logic signals, and they're
    > working fine.
    >
    > Thanks,
    > Rob
    >


    This might be related to a recent conversation on the P1076 reflector
    list (see below).

    I hope Paul & Jerry don't mind me reposting this,

    Hans.
    www.ht-lab.com



    Paul,
    This change was intentional and its main purpose was to reduce code
    bloat in standard and user packages.
    Typically, both implementations of function 'f' you have mentioned would
    be almost identical, the only difference being resolved/unresolved
    argument and/or result types. There are numerous examples in standard
    packages providing arithmetic operators and conversion functions where
    2008 versions are less than half the size of previous versions.
    The best practical (although not exactly standard) solution to your
    problem would be to use pragmas to exclude offending definitions from
    compilation in 2008 mode. I'm talking about something like this:
    --vhdl_comp_off -2008
    function f(x : std_logic_vector) return integer;
    --vhdl_comp_on
    function f(x : std_ulogic_vector) return integer;
    Otherwise, separate code base must be maintained for older versions of
    the standard.
    Thank you,
    Jerry

    On Thu, Aug 22, 2013 at 10:34 AM, Paul wrote:

    The vhdl-2008 std_logic_1164 package changes the definition of
    std_logic_vector. Previously it was a distinct type from
    std_ulogic_vector. In vhdl-2008 it is a subtype of std_ulogic_vector.
    This change is not backwards compatible as it can result in homograph
    conflicts. For instance:

    function f(x : std_logic_vector) return integer;
    function f(x : std_ulogic_vector) return integer;

    Pre-2008 these functions could coexist. In vhdl-2008 they are
    homographs and cannot coexist.

    Is this a known and expected incompatibility?

    Paul
    HT-Lab, Aug 23, 2013
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  3. Rob Gaddi

    Andy Guest

    These are two separate issues from the same language change.

    For 2008 (and on) the VHDL standard defines std_logic_vector as a resolved subtype of std_ulogic_vector. Before 2008, they were separate (albeit "closely related") types of arrays of std_logic and std_ulogic, respectively.

    This means that, for 2008-compliant tools, you can directly assign a std_ulogic_vector to/from a std_logic_vector. In short, SLV and SULV are now interoperable just like SL and SUL always have been.

    It also means that, for 2008-compliant tools, the signature recognition fortwo subprograms with the same signature except one uses SLV and the other SULV, now fails, causing an error if two such subprograms are available to choose from. This is because VHDL subprogram signature recognition uses thetypes of the arguments and return values, instead of the subtypes. Note that even in pre-2008 language versions, you could not have two subprograms with the only difference between them being of SL vs SUL arguments either. But since that restriction has been in place for a very long time, there aren't too many designs that violate it.

    The only thing I would make sure of in Rob's case is that 2008 compatibility is enabled for his quartus project. Most tools will continue to default to older versions of the standard for quite some time, since there are (minor) backward compatibility issues (2008 also added new reserved words, including some PSL keywords). If it is enabled, then this sure looks like a bug to me.

    Some simulators will allow you to compile different modules in the same simulation with different version settings, and still interoperate. I don't know if there is a way to do that for any synthesis tools, but it is becomingmore important.

    Hope this helps,

    Andy
    Andy, Aug 23, 2013
    #3
  4. Rob Gaddi

    Rob Gaddi Guest

    On Fri, 23 Aug 2013 09:45:27 -0700 (PDT)
    Andy <> wrote:
    >
    > It also means that, for 2008-compliant tools, the signature recognition for two subprograms with the same signature except one uses SLV and the other SULV, now fails, causing an error if two such subprograms are available to choose from. This is because VHDL subprogram signature recognition uses the types of the arguments and return values, instead of the subtypes. Note that even in pre-2008 language versions, you could not have two subprograms with the only difference between them being of SL vs SUL arguments either. But since that restriction has been in place for a very long time, there aren't too many designs that violate it.
    >
    > The only thing I would make sure of in Rob's case is that 2008 compatibility is enabled for his quartus project. Most tools will continue to default to older versions of the standard for quite some time, since there are (minor) backward compatibility issues (2008 also added new reserved words, including some PSL keywords). If it is enabled, then this sure looks like a bug to me.
    >
    > Some simulators will allow you to compile different modules in the same simulation with different version settings, and still interoperate. I don't know if there is a way to do that for any synthesis tools, but it is becoming more important.
    >
    > Hope this helps,
    >
    > Andy


    Thanks, it does. Quartus's VHDL-2008 support is lacking in a bunch of
    ways. There's no support for *_vector, no ?? operator, no automatic ??
    when using std_logic in an if statement, no unary logic reduction
    operators, the list goes on. Basically, they got the fixed point
    package working and called it a day.

    --
    Rob Gaddi, Highland Technology -- www.highlandtechnology.com
    Email address domain is currently out of order. See above to fix.
    Rob Gaddi, Aug 23, 2013
    #4
  5. Rob Gaddi

    Tricky Guest


    > Thanks, it does. Quartus's VHDL-2008 support is lacking in a bunch of
    > ways. There's no support for *_vector, no ?? operator, no automatic ??
    > when using std_logic in an if statement, no unary logic reduction
    > operators, the list goes on. Basically, they got the fixed point
    > package working and called it a day.
    >


    I think its worse than that - David Bishop got it working by creating a 1993 compatible version of the library. The Quartus 2008 VHDL "support" is a joke.
    Tricky, Sep 2, 2013
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