post map simulation: internal signals

Discussion in 'VHDL' started by tysunset, Jun 4, 2011.

  1. tysunset

    tysunset

    Joined:
    Jun 4, 2011
    Messages:
    1
    Hi,

    I try to probe the internal signals in post map (post translate, etc) simulations in Modelsim. Got the simulation working finally. But new problem is that I get lots of sub signal name for each object, mainly from simprim library of Xilinx. Example

    Object X
    Name:
    timingcheckson
    xon
    loc
    init
    addr
    o
    clk_ipad
    rst_ipad

    Can anyone please to explain me which name is exactly the one I want to probe?

    Gets really frustrated about it. And can't find any tutorial about that (will helpful if any link as well)

    Thanks a lot. Don't want to probe signals in Chipscope every time.
     
    tysunset, Jun 4, 2011
    #1
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  2. tysunset

    flymolo

    Joined:
    Jun 2, 2011
    Messages:
    10
    If you want to preserve design hierarchy through synthesis and place and route use XST -keep_hierarchy switch (you can acces this throug GUI: select top level entry, right click on Synthesize XST -> Process Properties -> Synthesis Options.

    If you want only a few signals to be preserved use signal attribute:
    http://www.xilinx.com/itp/xilinx7/books/data/docs/cgd/cgd0109_70.html#wp240141

    Notice that this could change the area and timing, especially if you preserve whole design. So i would suggest to use second option.
     
    flymolo, Jun 8, 2011
    #2
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