post PAR simulation with Xilinx Project Navigator: how?

Discussion in 'VHDL' started by ra, Aug 3, 2004.

  1. ra

    ra Guest

    Hi,
    I'm using Xilinx ISE 6.2, and I've a small VHDL project that went
    through PAR. I want to simulate the post PAR model, but I'm not sure how
    to. From the Project Navigator, I did generate the post PAR simulation
    model, which apparently is a vhd file containing the top level entity I
    designed. How do I apply the original testbench to this entity? If I try
    to add the new vhd file to the project I get an error, because an entity
    with the same name already exists. Must be simple, but I don't
    understand what the procedure is....


    thanks,
    ra
     
    ra, Aug 3, 2004
    #1
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