KJ said:
Yes, one of the outputs of place and route is a VHDL (or Verilog)
simulation model that incorporates expected propogation delays.
Which usually consists of the netlist in e.g. VHDL which comes from the
synthesis stage and an SDF (standard delay format) file which is in
EDIF file and contains min/typ/max timings for each instance. Using a
simulator like Modelsim, you can do the following:
- compile the (VHDL) netlist
- In your testbench, create a new architecture for the top entity of
the design (which is part of the testbench)
- Start modelsim. Instruct it to use the SDF file for the design and
max timing
- Run your tests
- Redo it with min.
Min/Max are sufficient if you simulate all possible stages in all
combinations. Since this is not possible for medium sized and big sized
designs, an additional static time analysis is required for ASICs.
Hubble.