problem about quartusII warning

[b82422]

Hi all:
I'm trying to implement a simple counter in to stratixII(EP2S60F672C5ES)device,when compling it shows"Warning: Found pins functioning as undefined clocks and/or memory enables. " ,and I defined the pin through timing analysis=>>clock setting, set the fmax=50Mhz(the oscillator freq)the warning has gone but when I download it to FPGA it's still not working,(The board is proved to be working fine),some problem with my code or something else ?

code for counter
library ieee;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter is
port(
Clock: in std_logic;
Reset: in std_logic;
Output: out std_logic_vector(0 to 3));
end Counter;

architecture Behavioral of Counter is
signal temp: std_logic_vector(0 to 3);
begin
process(Clock,Reset)
begin
if Reset='1' then
temp <= "0000";
elsif(Clock'event and Clock='1') then

if temp="1001" then
temp<="0000";
else
temp <= temp + 1;
Output <= temp;
end if;

end if;

end process;


end Behavioral;


I assigned the clock to system clock pin_p23 ,reset to a switch,and output to four LED,the led supposed to be flickering ,anything wrong with it?

btw,what's the *.pof file used for?