Problem in an ALU design

Discussion in 'VHDL' started by ashfaq2419, Jul 10, 2010.

  1. ashfaq2419

    ashfaq2419

    Joined:
    Jul 10, 2010
    Messages:
    4
    Location:
    Torino,Italy
    Hi,

    i am implementing a very simple and small ALU. basically i was a programmer of verilog but unfortunately i have to do this job in VHDL now. the code is written below:

    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    USE IEEE.NUMERIC_STD.ALL;
    USE IEEE.STD_LOGIC_ARITH.ALL;
    USE WORK.TYPE_ALU.ALL;

    ENTITY ALU IS
    PORT (
    FUNC : IN TYPE_OP;
    IN1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    IN2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    ALU_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
    END ALU;

    ARCHITECTURE BEHAVIOR OF ALU IS

    SIGNAL IN1_IN2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
    SIGNAL TEMP_OUT : STD_LOGIC_VECTOR(31 DOWNTO 0);
    SIGNAL TEMP1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
    SIGNAL TEMP2 : STD_LOGIC_VECTOR(31 DOWNTO 0);


    BEGIN

    -- VARIABLE V1 : INTEGER;
    -- VARIABLE V2 : INTEGER;

    P_ALU: PROCESS (FUNC,IN1,IN2)
    BEGIN
    TEMP1 <= IN1;
    TEMP2 <= IN2;

    CASE FUNC IS
    WHEN ADD|LDMEM|SDMEM|ADDI => TEMP_OUT <= TEMP1+TEMP2;
    WHEN SUBA|SUBI => TEMP_OUT <= TEMP1-TEMP2;
    WHEN LAND|LANDI => TEMP_OUT <= TEMP1 AND TEMP2;
    WHEN LOR|LORI => TEMP_OUT <= TEMP1 OR TEMP2;
    WHEN LXOR|LXORI => TEMP_OUT <= TEMP1 XOR TEMP2;
    WHEN LNOR|LNORI => TEMP_OUT <= NOT(TEMP1 OR TEMP2);
    WHEN SLT|SLTI => TEMP_OUT <= sxt((TEMP1 < TEMP2),32);
    WHEN SLLR => TEMP_OUT <= TEMP1 SLL TO_INTEGER(UNSIGNED(TEMP2));
    WHEN SRLR => TEMP_OUT <= TEMP1 SRL TO_INTEGER(UNSIGNED(TEMP2));
    WHEN OTHERS => TEMP_OUT <= (OTHERS=>'Z');
    END CASE;

    ALU_OUT <= TEMP_OUT;
    END PROCESS P_ALU;

    END BEHAVORAL;

    the problem is with the libraries. like i am also using '+' operator so i have to use the arithmatic library, likewise i am also making conversions from std_logic_vector to undigned integer so i need the unsigned library as well. similarly for SLL and SRL i need the numeric library. please help me if anybody can understand my problem.

    thanx to all of u in advance.

    regards,
    ashfaq ahmed
     
    ashfaq2419, Jul 10, 2010
    #1
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  2. ashfaq2419

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    It's probably best to only use
    IEEE.NUMERIC_STD.ALL;

    You will need to introduce temporary variables TEMP1, TEMP2, TEMP_OUT (instead of the signals you have currently!), with type UNSIGNED(31 DOWNTO 0);
    Using signals in a process won't work as you intended (ofcourse, it is possible to use signals in a process, but only if you understand the semantics well enough)

    You don't need the sxt function, you can replace it with a simple if statement (this won't make any functional difference)

    This seems to work -- or at least it doesn't give syntax errors:
    Code:
    
    LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.NUMERIC_STD.ALL;
    USE WORK.TYPE_ALU.ALL;
    
    ENTITY ALU IS
    PORT (
    FUNC : IN TYPE_OP;
    IN1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    IN2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    ALU_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
    END ALU;
    
    ARCHITECTURE BEHAVIORAL OF ALU IS
    
    BEGIN
    
    P_ALU: PROCESS (FUNC,IN1,IN2)
    variable TEMP_OUT : unsigned(31 DOWNTO 0);
    variable TEMP1 : unsigned(31 DOWNTO 0);
    variable TEMP2 : unsigned(31 DOWNTO 0);
    
    BEGIN
    TEMP1 := unsigned(IN1);
    TEMP2 := unsigned(IN2);
    
    CASE FUNC IS
    WHEN ADD|LDMEM|SDMEM|ADDI => TEMP_OUT := TEMP1+TEMP2;
    WHEN SUBA|SUBI => TEMP_OUT := TEMP1-TEMP2;
    WHEN LAND|LANDI => TEMP_OUT := TEMP1 AND TEMP2;
    WHEN LOR|LORI => TEMP_OUT := TEMP1 OR TEMP2;
    WHEN LXOR|LXORI => TEMP_OUT := TEMP1 XOR TEMP2;
    WHEN LNOR|LNORI => TEMP_OUT := TEMP1 NOR TEMP2;
    WHEN SLT|SLTI => 
      if (TEMP1 < TEMP2) then
        TEMP_OUT := (0 => '1', others => '0');
      else
        TEMP_OUT := (others => '0');
      end if;
    WHEN SLLR => TEMP_OUT := TEMP1 SLL TO_INTEGER(TEMP2);
    WHEN SRLR => TEMP_OUT := TEMP1 SRL TO_INTEGER(TEMP2);
    WHEN OTHERS => TEMP_OUT := (OTHERS=>'Z');
    END CASE;
    
    ALU_OUT <= STD_LOGIC_VECTOR(TEMP_OUT);
    END PROCESS P_ALU;
    
    END BEHAVIORAL;
    
     
    joris, Jul 10, 2010
    #2
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