Problem in array formation

Discussion in 'VHDL' started by vedpsingh@gmail.com, May 5, 2005.

  1. Guest

    Hello all !
    Please see the codes given below, just compile them and coonect them as
    per the following connectivity :

    ----------------------------------------------------------------------------
    clock and reset are the only inputs.

    clock16x16:
    out_clk => flag_intr of (interlvr_behav)

    count_ext => to all count_ext inputs

    rom_data_behav:
    Q => syst_data of (interlvr_behav)

    rom_interlvr_interlvr
    Q => PN_seq_index of (interlvr_behav)




    ----------------------------------------------------------------------------
    There are in all 4 codes.

    (1)clock16x16 ----------> is just a simple control block

    (2)rom_data_behav -------> supplies a 16 bit data for test purpose.

    (3)rom_interlvr_interlvr ----> just an indexing data provider

    (4)interleaver_behav ------> is the block where my problem exists.
    Here, I want to make array's hold_seq1 and hold_seq2

    according
    to index given by the signal count_ext. The zero'th element in the
    array hold_seq1 misses the value !!! and the sequence

    coming from syst_data does not get filled up correctly.
    So what I want is that the locations from 0 to 13 of array hold_seq
    sould have the 0 to 13 value as in the rom_data_behav,

    while locations 14 and 15 of hold_seq should have value coming from the
    fr_in_ser i.e.

    hold_seq(0) <= syst_data0
    hold_seq(1) <= syst_data1
    hold_seq(1) <= syst_data2
    , May 5, 2005
    #1
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