Problem in design

Discussion in 'VHDL' started by Deepa, Jun 24, 2005.

  1. Deepa

    Deepa Guest

    Hello there!
    I want to read a memory containing 4096 words(altsyncram named R,G,B.
    used a MIF file to store the data) and convert them to YUV. I have
    checked yuv conversion. It works. But in Quartus the Analysis and
    Synthesis hangs at 10%. I will be happy if anybody helps me out.

    ENTITY PRO1 IS
    PORT(START,CLK:IN STD_LOGIC;
    FIN_STEP1:OUT STD_LOGIC;
    FIN_STEP2: OUT STD_LOGIC);
    END ENTITY PRO1;
    ------------------------------------------
    ARCHITECTURE A OF PRO1 IS
    ------------------------------------------
    TYPE YUVARRAY IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
    SHARED VARIABLE Y1,U1,V1 : YUVARRAY;
    SIGNAL RDATA,GDATA,BDATA,ROUT,BOUT,GOUT,Y,U,V: STD_LOGIC_VECTOR(7
    DOWNTO 0);
    SIGNAL RW,GW,BW: STD_LOGIC;
    SIGNAL STEP1,FINRGB:STD_LOGIC;
    SIGNAL RWAD,BWAD,GWAD,RRAD,GRAD,BRAD:STD_LOGIC_VECTOR(11 DOWNTO 0);
    SHARED VARIABLE I,RED,GREEN,BLUE : INTEGER;
    -------------------------------------------
    COMPONENT RGB2YUV IS
    port(START_CONV:in std_logic;
    RED,GREEN,BLUE: in std_logic_vector(7 downto 0);
    Y,U,V: out std_logic_vector(7 downto 0);
    FIN_CONV: out std_logic);
    END COMPONENT RGB2YUV;
    -------------------------------------------
    COMPONENT B IS
    PORT
    (
    data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    wren : IN STD_LOGIC := '1';
    wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    clock : IN STD_LOGIC ;
    q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    );
    END COMPONENT B;
    -------------------------------------------
    COMPONENT G IS
    PORT
    (
    data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    wren : IN STD_LOGIC := '1';
    wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    clock : IN STD_LOGIC ;
    q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    );
    END COMPONENT G;
    -------------------------------------------
    COMPONENT R IS
    PORT
    (
    data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    wren : IN STD_LOGIC := '1';
    wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    clock : IN STD_LOGIC ;
    q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    );
    END COMPONENT R;
    -------------------------------------------
    BEGIN
    STAGE1: RGB2YUV PORT MAP(STEP1,ROUT,GOUT,BOUT,Y,U,V,FINRGB);
    RROM: R PORT MAP(RDATA,RW,RWAD,RRAD,CLK,ROUT);
    GROM: G PORT MAP(GDATA,GW,GWAD,GRAD,CLK,GOUT);
    BROM: B PORT MAP(BDATA,BW,BWAD,BRAD,CLK,BOUT);
    -------------------------------------------
    S1:pROCESS(START,FINRGB)
    BEGIN
    RED:=0;GREEN:=0;BLUE:=0;
    STEP1<='0';FIN_STEP1<='0';
    IF(START = '1') THEN
    RW<='0';GW<='0';BW<='0';

    CONVRGB:FOR I IN 0 TO 4095 LOOP
    RRAD<=INT2SLVECT(I,12);GRAD<=INT2SLVECT(I,12);BRAD<=INT2SLVECT(I,12);

    -- RED:=SLVECT2INT(ROUT,8);GREEN:=SLVECT2INT(GOUT,8);BLUE:=SLVECT2INT(BOUT,8);
    STEP1<='1';
    --RWAD<=RRAD;BWAD<=BRAD;GWAD<=BRAD;
    --RW<='1';GW<='1';BW<='1';
    --RDATA<=Y;GDATA<=U;BDATA<=V;
    --Y1(I):=SLVECT2INT(Y,8);Y2(I):=SLVECT2INT(U,8);Y3(I):=SLVECT2INT(V,8);
    --STEP1<='0';
    Y1(I):=Y;U1(I):=U;V1(I):=V;
    END LOOP CONVRGB;
    FIN_STEP1<='1';
    END IF;
    END PROCESS S1;
    END ARCHITECTURE A;
    Deepa, Jun 24, 2005
    #1
    1. Advertising

  2. Deepa

    Guest

    Deepa,
    Shared variables are not synthesizable.Functions
    INT2SLVECT,SLVECT2INT are not visible. The code is more of like C prog
    code. Statements in the procees construct seem to be hardware
    intensive. Better consult who knows RTL coding in your office/college.
    Cheers,
    Raghavendra.

    Deepa wrote:
    > Hello there!
    > I want to read a memory containing 4096 words(altsyncram named R,G,B.
    > used a MIF file to store the data) and convert them to YUV. I have
    > checked yuv conversion. It works. But in Quartus the Analysis and
    > Synthesis hangs at 10%. I will be happy if anybody helps me out.
    >
    > ENTITY PRO1 IS
    > PORT(START,CLK:IN STD_LOGIC;
    > FIN_STEP1:OUT STD_LOGIC;
    > FIN_STEP2: OUT STD_LOGIC);
    > END ENTITY PRO1;
    > ------------------------------------------
    > ARCHITECTURE A OF PRO1 IS
    > ------------------------------------------
    > TYPE YUVARRAY IS ARRAY(0 TO 4095) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
    > SHARED VARIABLE Y1,U1,V1 : YUVARRAY;
    > SIGNAL RDATA,GDATA,BDATA,ROUT,BOUT,GOUT,Y,U,V: STD_LOGIC_VECTOR(7
    > DOWNTO 0);
    > SIGNAL RW,GW,BW: STD_LOGIC;
    > SIGNAL STEP1,FINRGB:STD_LOGIC;
    > SIGNAL RWAD,BWAD,GWAD,RRAD,GRAD,BRAD:STD_LOGIC_VECTOR(11 DOWNTO 0);
    > SHARED VARIABLE I,RED,GREEN,BLUE : INTEGER;
    > -------------------------------------------
    > COMPONENT RGB2YUV IS
    > port(START_CONV:in std_logic;
    > RED,GREEN,BLUE: in std_logic_vector(7 downto 0);
    > Y,U,V: out std_logic_vector(7 downto 0);
    > FIN_CONV: out std_logic);
    > END COMPONENT RGB2YUV;
    > -------------------------------------------
    > COMPONENT B IS
    > PORT
    > (
    > data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    > wren : IN STD_LOGIC := '1';
    > wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    > rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    > clock : IN STD_LOGIC ;
    > q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    > );
    > END COMPONENT B;
    > -------------------------------------------
    > COMPONENT G IS
    > PORT
    > (
    > data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    > wren : IN STD_LOGIC := '1';
    > wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    > rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    > clock : IN STD_LOGIC ;
    > q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    > );
    > END COMPONENT G;
    > -------------------------------------------
    > COMPONENT R IS
    > PORT
    > (
    > data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
    > wren : IN STD_LOGIC := '1';
    > wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    > rdaddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
    > clock : IN STD_LOGIC ;
    > q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
    > );
    > END COMPONENT R;
    > -------------------------------------------
    > BEGIN
    > STAGE1: RGB2YUV PORT MAP(STEP1,ROUT,GOUT,BOUT,Y,U,V,FINRGB);
    > RROM: R PORT MAP(RDATA,RW,RWAD,RRAD,CLK,ROUT);
    > GROM: G PORT MAP(GDATA,GW,GWAD,GRAD,CLK,GOUT);
    > BROM: B PORT MAP(BDATA,BW,BWAD,BRAD,CLK,BOUT);
    > -------------------------------------------
    > S1:pROCESS(START,FINRGB)
    > BEGIN
    > RED:=0;GREEN:=0;BLUE:=0;
    > STEP1<='0';FIN_STEP1<='0';
    > IF(START = '1') THEN
    > RW<='0';GW<='0';BW<='0';
    >
    > CONVRGB:FOR I IN 0 TO 4095 LOOP
    > RRAD<=INT2SLVECT(I,12);GRAD<=INT2SLVECT(I,12);BRAD<=INT2SLVECT(I,12);
    >
    > -- RED:=SLVECT2INT(ROUT,8);GREEN:=SLVECT2INT(GOUT,8);BLUE:=SLVECT2INT(BOUT,8);
    > STEP1<='1';
    > --RWAD<=RRAD;BWAD<=BRAD;GWAD<=BRAD;
    > --RW<='1';GW<='1';BW<='1';
    > --RDATA<=Y;GDATA<=U;BDATA<=V;
    > --Y1(I):=SLVECT2INT(Y,8);Y2(I):=SLVECT2INT(U,8);Y3(I):=SLVECT2INT(V,8);
    > --STEP1<='0';
    > Y1(I):=Y;U1(I):=U;V1(I):=V;
    > END LOOP CONVRGB;
    > FIN_STEP1<='1';
    > END IF;
    > END PROCESS S1;
    > END ARCHITECTURE A;
    , Jun 24, 2005
    #2
    1. Advertising

  3. Deepa

    Neo Guest

    There is as such nothing wrong with your code except that it is very
    unwieldy. You have got a huge array and a lot of conversion in loops.
    So it is going to take plenty of time or if not enough memory it will
    hang. But I dont see the need for shared variables.
    Neo, Jun 24, 2005
    #3
  4. Deepa

    Deepa Guest

    Thanks for your replies. I have another doubt. I can't see the value of
    variables using quartus II. I have stored the YUV values in the RAM
    itself. So will the mif file be updated by those values? How can I see
    the RAM data after the simulation?
    Deepa, Jun 27, 2005
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. ZackS
    Replies:
    5
    Views:
    6,794
    Just an Illusion
    Jul 9, 2004
  2. SpamProof
    Replies:
    3
    Views:
    642
    SpamProof
    Dec 1, 2003
  3. dave
    Replies:
    5
    Views:
    589
    William Brogden
    Jul 17, 2004
  4. Tim Smith
    Replies:
    2
    Views:
    854
    Tim Smith
    Dec 15, 2004
  5. trint
    Replies:
    1
    Views:
    357
    trint
    Nov 21, 2006
Loading...

Share This Page