problem in vhdl code with a one clock delay

P

Pieter

I'am a student in belgium and for an project in school. I've got to
make an project with a virtex II pro and the program is write in VHDL.
The purpose of the project is to make an vhdl-code so that an composite
signal is translated to an RGB signal to send to a VGA screen, like a
computer screen.
In one of the sub program i' have following problem :

There is an 10-bits input signal and a clock input. The program will
scan the 10-bits input signal and when the code FF 00 00 is detected
than the program will send bit 8 to and output. But the problem is now
that he sends it a clock pulse to late, so theres a clock pulse delay
when he detected it and when it sends it to the output. The program is
the following :

signal TRS : std_logic;
signal A,B,C : std_logic;
signal Fo_in : std_logic;

if rising_edge(clk) then
if YCrCb_rg2(9 downto 2) = "00000000" then--00
A := '1';
else
A := '0';
end if;

if YCrCb_rg3(9 downto 2) = "00000000" then--00
B := '1';
else
B := '0';
end if;

if YCrCb_rg4(9 downto 2) = "11111111" then--FF
C := '1';
else
C := '0';
end if;
end if;

if rst= '1' then
Fo_in <= '0';
elsif TRS = '1' then
Fo_in <= YCrCb_rg1(8);
end if;

TRS := A AND B AND C;
Fo <= Fo_in; --send to the ouput pin

Should i use variables instead of signals maybe?? Thanks in advance and
hope that you understand my english a bit.
 
K

KJ

Pieter said:
I'am a student in belgium and for an project in school. I've got to
make an project with a virtex II pro and the program is write in VHDL.
The purpose of the project is to make an vhdl-code so that an composite
signal is translated to an RGB signal to send to a VGA screen, like a
computer screen.
In one of the sub program i' have following problem :

There is an 10-bits input signal and a clock input. The program will
scan the 10-bits input signal and when the code FF 00 00 is detected
than the program will send bit 8 to and output. But the problem is now
that he sends it a clock pulse to late, so theres a clock pulse delay
when he detected it and when it sends it to the output. The program is
the following :
Click to expand...

If the outputs need to happen on the same clock cycle as the inputs, then
there is no need for a clock signal. The outputs should be combinatorial
outputs so simply get rid of the "if rising_edge(clk) then" (and the
corresponding "end if").

Below is a snippet of your code
signal A,B,C : std_logic;
signal Fo_in : std_logic;
if rising_edge(clk) then
if YCrCb_rg2(9 downto 2) = "00000000" then--00
A := '1';
else
A := '0';
end if;
Click to expand...

And what it should be to get signal 'A' out on the same clock cycle.
A<:= '1' when (YCrCb_rg2(9 downto 2) = "00000000") else '0'

The other signals would convert in the same manner.

KJ
 
M

Mike Treseler

Pieter said:
Should i use variables instead of signals maybe?? Thanks in advance and
hope that you understand my english a bit.
Click to expand...

The variable assignment operator :=
requires a variable on the left side.
Synthesis requires code to match
a template like this:

process(reset, clock) is
-- variable declarations here
begin
if reset = '1' then
init_regs;
elsif rising_edge(clock) then
update_regs;
end if;
update_ports;
end process sync_template;
end architecture synth;

See full examples here:
http://home.comcast.net/~mike_treseler/

-- Mike Treseler
 
K

KJ

Slight typo
A<:= '1' when (YCrCb_rg2(9 downto 2) = "00000000") else '0' --
Oops....A<:= is not valid
Click to expand...

should be

A<= '1' when (YCrCb_rg2(9 downto 2) = "00000000") else '0';

By the way, in your original code you had A:= .... but since A was defined
to be a signal the assignment must be A<= ...

KJ
 
A

Andy

Actually, synthesis tools do not _require_ the asynchronous reset
clause at the beginning (i.e. in an if-elsif before the
rising_edge(clk) condition). The reset clause can be in a separate if
statement, following the clock condition clause.

This is the only way to code if you need some registered resources to
be asynchronously reset, while not resetting others (like rams, etc.)
in the same process.

Using Mike's example:

process (rst, clk) is
-- variable and procedure declarations here
begin
if rising_edge(clk) then -- clocked logic clause
update_regs;
end if;
if rst = '1' then -- async reset clause
init_regs;
end if;
update_ports;
end process;


Andy
 
M

Mike Treseler

Andy said:
Actually, synthesis tools do not _require_ the asynchronous reset
clause at the beginning (i.e. in an if-elsif before the
rising_edge(clk) condition).
Click to expand...

Good point. My intent was just to show Pieter
where to put the variable declarations,
not to imply that there is only one
synthesis template.

-- Mike Treseler
 
D

Dave Pollum

Pieter said:
I'am a student in belgium and for an project in school. I've got to
make an project with a virtex II pro and the program is write in VHDL.
The purpose of the project is to make an vhdl-code so that an composite
signal is translated to an RGB signal to send to a VGA screen, like a
computer screen.
In one of the sub program i' have following problem :

There is an 10-bits input signal and a clock input. The program will
scan the 10-bits input signal and when the code FF 00 00 is detected
than the program will send bit 8 to and output. But the problem is now
that he sends it a clock pulse to late, so theres a clock pulse delay
when he detected it and when it sends it to the output. The program is
the following :

signal TRS : std_logic;
signal A,B,C : std_logic;
signal Fo_in : std_logic;

if rising_edge(clk) then
if YCrCb_rg2(9 downto 2) = "00000000" then--00
A := '1';
else
A := '0';
end if;

if YCrCb_rg3(9 downto 2) = "00000000" then--00
B := '1';
else
B := '0';
end if;

if YCrCb_rg4(9 downto 2) = "11111111" then--FF
C := '1';
else
C := '0';
end if;
end if;

if rst= '1' then
Fo_in <= '0';
elsif TRS = '1' then
Fo_in <= YCrCb_rg1(8);
end if;

TRS := A AND B AND C;
Fo <= Fo_in; --send to the ouput pin

Should i use variables instead of signals maybe?? Thanks in advance and
hope that you understand my english a bit.
Click to expand...

if rst= '1' then
Fo_in <= '0';
elsif TRS = '1' then
Fo_in <= YCrCb_rg1(8);
end if;

Unless I'm mistaken, a latch is created for "Fo_in", because there is
no "else" clause. I don't know if this is related to your problem or
not.

HTH
-Dave Pollum
 
P

Pieter

If I copy this to the program and I check the syntax, then the program
gives an error.

A <= '1' when (YCrCb_rg2(9 downto 2) = "00000000") else '0';

Are you shure thats this line works in vhdl??

Thanks Pieter
 
K

KJ

Pieter said:
If I copy this to the program and I check the syntax, then the program
gives an error.

A <= '1' when (YCrCb_rg2(9 downto 2) = "00000000") else '0';

Are you shure thats this line works in vhdl??
Click to expand...
The following snippet of code compiles just fine using Modelsim. Go
back and read the error message that is being reported and fix your
code accordingly.

signal A: std_logic;
signal YCrCb_rg2: std_ulogic_vector(9 downto 0);
begin

A <= '1' when (YCrCb_rg2(9 downto 2) = "00000000") else '0';

KJ
 
B

Ben Twijnstra

Pieter said:
If I copy this to the program and I check the syntax, then the program
gives an error.

A <= '1' when (YCrCb_rg2(9 downto 2) = "00000000") else '0';

Are you shure thats this line works in vhdl??
Click to expand...

If you do this in an architecture body, and outside a process, this should
work - it looks like a valid concurrent statement.

Best regards,


Ben
 
J

Jelmer

Maybe your whole program is not concurrent.
Try to put all sequences in a process...
I think your problem should be resolved...
 
P

Pieter

Jelmer schreef:
Maybe your whole program is not concurrent.
Try to put all sequences in a process...
I think your problem should be resolved...
Click to expand...

I tried it, at now its works like it should be.

Thanks a lot
 
M

Mike Treseler

Andy said:
Actually, synthesis tools do not _require_ the asynchronous reset
clause at the beginning (i.e. in an if-elsif before the
rising_edge(clk) condition). The reset clause can be in a separate if
statement, following the clock condition clause.
This is the only way to code if you need some registered resources to
be asynchronously reset, while not resetting others (like rams, etc.)
in the same process.
Using Mike's example:

process (rst, clk) is
-- variable and procedure declarations here
begin
if rising_edge(clk) then -- clocked logic clause
update_regs;
end if;
if rst = '1' then -- async reset clause
init_regs;
end if;
update_ports;
end process;
Click to expand...

I just tried out Andy's template above
and it works fine in simulation and synthesis.
For details find "so_rst" in the reference design here:

http://home.comcast.net/~mike_treseler/


-- Mike Treseler


_________________________
vsim -Gtemplate_g=so_rst -c test_uart -do "run -all; exit"

Reading /flip/usr1/modeltech/tcl/vsim/pref.tcl
# 6.2a
# vsim -do {run -all; exit} -c -Gtemplate_g=so_rst test_uart
# Loading /flip/usr1/modeltech/linux/../std.standard
# Loading /flip/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /flip/usr1/modeltech/linux/../ieee.numeric_std(body)
# Loading work.uart_pkg
# Loading work.test_uart(sim)#1
# Loading work.uart(templates)#1
# run -all
# ** Note: Saw reset rise and fall OK
# Time: 105 ns Iteration: 1 Instance: /test_uart
# ** Note: Using fixed_delay_c = 1080 ns That's 108 ticks.
# Time: 105 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 0
# Time: 1275 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 36 as expected
# Time: 1275 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 1
# Time: 2445 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 199 as expected
# Time: 2445 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 2
# Time: 3615 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 24 as expected
# Time: 3615 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 3
# Time: 4785 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 131 as expected
# Time: 4785 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 4
# Time: 5955 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 211 as expected
# Time: 5955 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 5
# Time: 7125 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 217 as expected
# Time: 7125 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 6
# Time: 8295 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 58 as expected
# Time: 8295 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 7
# Time: 9465 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 229 as expected
# Time: 9465 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 8
# Time: 9885 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 229 as expected
# Time: 9885 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 9
# Time: 10305 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 131 as expected
# Time: 10305 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 10
# Time: 10725 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 46 as expected
# Time: 10725 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 11
# Time: 11145 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 217 as expected
# Time: 11145 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 12
# Time: 11565 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 199 as expected
# Time: 11565 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 13
# Time: 11985 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 229 as expected
# Time: 11985 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 14
# Time: 12405 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 131 as expected
# Time: 12405 ns Iteration: 1 Instance: /test_uart
# ** Note: ___Step 15
# Time: 12825 ns Iteration: 1 Instance: /test_uart
# ** Note: ____________ saw 46 as expected
# Time: 12825 ns Iteration: 1 Instance: /test_uart
# ** Note: ___ALL PASS___
# Time: 12825 ns Iteration: 1 Instance: /test_uart
# exit
71 Thu Dec 21 /evtfs/home/tres/vhdl/ref_design>
 

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