problem on structural architcture

Discussion in 'VHDL' started by new_user, Nov 26, 2007.

  1. new_user

    new_user

    Joined:
    Nov 26, 2007
    Messages:
    1
    hi guy, I'm new to the VHDL. I trying, without succeed to finish my project. I need some help :p.. It will take a bit to explane, just be patience and read the following... i will try to be as much clear as possible :)

    I have to implement a behavioural and structural architecture of the following:
    entity log_1_p_x_div_1_m_x is
    port (x : in signed(15 downto 0);
    y : out signed(23 downto 0));
    end entity;

    it can be approssimated by the equation:
    y = 2x*(1+ x^2 *(1/3 + x^2 *(1/5 + 1/7*x^2)))

    As u can see there are just product and sum, the x is in the range (-1, 1)
    the behavioral is done, i attached some files :p
    The code of behavioral architecture simulate also a pipeline system.

    The problem is with the stuctural architecture.
    Anybody have a idea how to do it? Or somebody have some example with the data type signed!! I think the problem is with this signed data type, related with the data format.
    The input x is in format Q1.15 and the output will be in the Q5.19.
    In the stuctural arch. there will be 3 adder, 5 multiplier to obtain a Q4.28 (assuming to have a 32 bit after the first multiplication, and use just those one, the others will be cuted). At the end i will have a shift that will bring the output at Q5.27, and i will pass just the more important bit :)

    How to make the adder with signed?

    Thanks a lot for the help!
    If u can just wirte me soon :)
    Ciao

    PS. I added also some nice draw and the half of the code of the struct!
     

    Attached Files:

    new_user, Nov 26, 2007
    #1
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